llvm/CodeGen at 5882e3d82831710a7ea1fe8de4813350d4eecf05 - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-02-08 19:46:39 +00:00

History

Ulrich Weigand 5882e3d828 Rewrite pre-increment store patterns to use standard memory operands.

Currently, pre-increment store patterns are written to use two separate
operands to represent address base and displacement:

  stwu $rS, $ptroff($ptrreg)

This causes problems when implementing the assembler parser, so this
commit changes the patterns to use standard (complex) memory operands
like in all other memory access instruction patterns:

  stwu $rS, $dst

To still match those instructions against the appropriate pre_store
SelectionDAG nodes, the patch uses the new feature that allows a Pat
to match multiple DAG operands against a single (complex) instruction
operand.

Approved by Hal Finkel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429 91177308-0d34-0410-b5e6-96231b3b80d8

2013-03-19 19:52:04 +00:00

AArch64

Test case hygiene.

2013-03-09 18:25:40 +00:00

ARM

Improve long vector sext/zext lowering on ARM

2013-03-19 08:15:38 +00:00

CPP

test commit: remove blank line.

2013-03-14 05:43:59 +00:00

Generic

For inline asm: