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Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MTHC1 to be scheduled on the wrong side of most 32-bit FPU ops, particularly MTC1. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. The testcase is SingleSource/Benchmarks/Misc/oourafft.c when given TARGET_CFLAGS='-mips32r2 mfp64 -mmsa'. Also correct the comment added in r203464 to indicate that two instructions were affected. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3029 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203659 91177308-0d34-0410-b5e6-96231b3b80d8
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