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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
1.6 KiB
LLVM
38 lines
1.6 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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; CHECK: S_ENDPGM
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define void @main() {
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main_body:
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call void @llvm.AMDGPU.shader.type(i32 1)
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%0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*)
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%1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0
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%2 = load <4 x i32> addrspace(2)* %1
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%3 = call i32 @llvm.SI.vs.load.buffer.index()
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%4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3)
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%5 = extractelement <4 x float> %4, i32 0
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%6 = extractelement <4 x float> %4, i32 1
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%7 = extractelement <4 x float> %4, i32 2
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%8 = extractelement <4 x float> %4, i32 3
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%9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*)
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%10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1
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%11 = load <4 x i32> addrspace(2)* %10
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%12 = call i32 @llvm.SI.vs.load.buffer.index()
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%13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12)
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%14 = extractelement <4 x float> %13, i32 0
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%15 = extractelement <4 x float> %13, i32 1
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%16 = extractelement <4 x float> %13, i32 2
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%17 = extractelement <4 x float> %13, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17)
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %5, float %6, float %7, float %8)
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ret void
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}
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declare void @llvm.AMDGPU.shader.type(i32)
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declare i32 @llvm.SI.vs.load.buffer.index() readnone
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declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32)
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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