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8e2e335276
Now that we are generating sane codegen for vector sext/zext nodes on SSE targets, this patch uses instcombine to replace the SSE41/AVX2 pmovsx and pmovzx intrinsics with the equivalent native IR code. Differential Revision: http://reviews.llvm.org/D11503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243303 91177308-0d34-0410-b5e6-96231b3b80d8
137 lines
4.9 KiB
LLVM
137 lines
4.9 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone
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declare <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8>) nounwind readnone
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declare <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32>) nounwind readnone
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declare <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16>) nounwind readnone
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;
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; Basic zero extension tests
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;
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define <4 x i32> @sse41_pmovzxbd(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxbd
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: zext <4 x i8> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %v)
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ret <4 x i32> %res
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}
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define <2 x i64> @sse41_pmovzxbq(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxbq
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: zext <2 x i8> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %v)
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ret <2 x i64> %res
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}
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define <8 x i16> @sse41_pmovzxbw(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxbw
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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; CHECK-NEXT: zext <8 x i8> %1 to <8 x i16>
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; CHECK-NEXT: ret <8 x i16> %2
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%res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %v)
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ret <8 x i16> %res
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}
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define <2 x i64> @sse41_pmovzxdq(<4 x i32> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxdq
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; CHECK-NEXT: shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: zext <2 x i32> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %v)
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ret <2 x i64> %res
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}
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define <4 x i32> @sse41_pmovzxwd(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxwd
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; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: zext <4 x i16> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %v)
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ret <4 x i32> %res
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}
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define <2 x i64> @sse41_pmovzxwq(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxwq
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; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: zext <2 x i16> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %v)
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ret <2 x i64> %res
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}
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define <8 x i32> @avx2_pmovzxbd(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovzxbd
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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; CHECK-NEXT: zext <8 x i8> %1 to <8 x i32>
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; CHECK-NEXT: ret <8 x i32> %2
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%res = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %v)
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ret <8 x i32> %res
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}
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define <4 x i64> @avx2_pmovzxbq(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovzxbq
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: zext <4 x i8> %1 to <4 x i64>
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; CHECK-NEXT: ret <4 x i64> %2
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%res = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %v)
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ret <4 x i64> %res
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}
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define <16 x i16> @avx2_pmovzxbw(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovzxbw
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; CHECK-NEXT: zext <16 x i8> %v to <16 x i16>
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; CHECK-NEXT: ret <16 x i16> %1
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%res = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %v)
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ret <16 x i16> %res
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}
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define <4 x i64> @avx2_pmovzxdq(<4 x i32> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovzxdq
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; CHECK-NEXT: zext <4 x i32> %v to <4 x i64>
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; CHECK-NEXT: ret <4 x i64> %1
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%res = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %v)
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ret <4 x i64> %res
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}
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define <8 x i32> @avx2_pmovzxwd(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovzxwd
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; CHECK-NEXT: zext <8 x i16> %v to <8 x i32>
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; CHECK-NEXT: ret <8 x i32> %1
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%res = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %v)
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ret <8 x i32> %res
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}
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define <4 x i64> @avx2_pmovzxwq(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovzxwq
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; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: zext <4 x i16> %1 to <4 x i64>
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; CHECK-NEXT: ret <4 x i64> %2
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%res = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %v)
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ret <4 x i64> %res
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}
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