Simon Dardis dbc69646c5 [mips] interAptiv based generic schedule model ...

This scheduler describes a processor which covers all MIPS ISAs based
around the interAptiv and P5600 timings.

Reviewers: vkalintiris, dsanders

Differential Revision: https://reviews.llvm.org/D23551


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280374 91177308-0d34-0410-b5e6-96231b3b80d8

2016-09-01 14:53:53 +00:00

..

delay-slot.ll

[mips][ias] Only round section sizes when explicitly requested.

2016-05-04 13:21:06 +00:00

dsr-fixed-objects.ll

[mips] interAptiv based generic schedule model

2016-09-01 14:53:53 +00:00

dsr-non-fixed-objects.ll

[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.

2016-04-15 15:57:41 +00:00

fn-call-line.ll

[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.

2016-04-15 15:57:41 +00:00

InlinedFnLocalVar.ll

Reverting 268054 & 268063 as they caused PR27579.

2016-04-30 01:44:07 +00:00

lit.local.cfg

…

processes-relocations.ll

…

prologue_end.ll

[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.

2016-04-15 15:57:41 +00:00