Jakob Stoklund Olesen 5f2316a3b5 Switch AllocationOrder to using RegisterClassInfo instead of a BitVector ...

of reserved registers.

Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8

2011-06-03 20:34:53 +00:00

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Alpha

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ARM

Make the Uv constraint a memory operand. This doesn't solve the

2011-06-03 17:24:37 +00:00

Blackfin

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CBackend

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CellSPU

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CPP

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Generic

This patch is another step in the direction of adding vector select. In this

2011-06-01 12:51:46 +00:00

MBlaze

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Mips

Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.

2011-06-02 01:03:14 +00:00

MSP430

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PowerPC

Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.

2011-06-03 15:47:49 +00:00

PTX

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SPARC

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SystemZ

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Thumb

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Thumb2

Switch AllocationOrder to using RegisterClassInfo instead of a BitVector

2011-06-03 20:34:53 +00:00

X86

Add test for PR10068.

2011-06-02 20:02:48 +00:00

XCore

Add XCore intrinsic for crc8.

2011-05-31 16:24:49 +00:00