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c8e7045c8a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169325 91177308-0d34-0410-b5e6-96231b3b80d8
192 lines
6.0 KiB
LLVM
192 lines
6.0 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; Implement ctpop with vcnt
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define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
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;CHECK: vcnt8:
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;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
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;CHECK: vcntQ8:
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;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
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ret <16 x i8> %tmp2
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}
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define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
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; CHECK: vcnt16:
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; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vuzp.8 {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
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; CHECK: vcntQ16:
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; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vuzp.8 {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
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; CHECK: vcnt32:
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; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vuzp.8 {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
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; CHECK: vrev32.16 {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vuzp.16 {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
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; CHECK: vcntQ32:
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; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vuzp.8 {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
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; CHECK: vrev32.16 {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vuzp.16 {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
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declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone
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declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
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define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
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;CHECK: vclz8:
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;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
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;CHECK: vclz16:
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;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
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;CHECK: vclz32:
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;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
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ret <2 x i32> %tmp2
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}
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define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
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;CHECK: vclzQ8:
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;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
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;CHECK: vclzQ16:
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;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
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;CHECK: vclzQ32:
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;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
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ret <4 x i32> %tmp2
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}
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declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
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declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
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declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
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declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
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declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
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declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
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define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
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;CHECK: vclss8:
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;CHECK: vcls.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
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;CHECK: vclss16:
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;CHECK: vcls.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
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;CHECK: vclss32:
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;CHECK: vcls.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
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;CHECK: vclsQs8:
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;CHECK: vcls.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
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;CHECK: vclsQs16:
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;CHECK: vcls.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
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;CHECK: vclsQs32:
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;CHECK: vcls.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) nounwind readnone
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