Matt Arsenault 6241a83e35 AMDGPU: Restrict extract_vector_elt combine to loads ...

The intention is to enable the extract_vector_elt load combine,
and doing this for other operations interferes with more
useful optimizations on vectors.

Handle any type of load since in principle we should do the
same combine for the various load intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341219 91177308-0d34-0410-b5e6-96231b3b80d8

2018-08-31 15:39:52 +00:00

..

AArch64

[NFC][X86][AArch64] A few more patterns for [lack of] signed truncation check pattern.[NFC][X86][AArch64] A few more patterns for [lack of] signed truncation check pattern.

2018-08-31 08:52:03 +00:00

AMDGPU

AMDGPU: Restrict extract_vector_elt combine to loads

2018-08-31 15:39:52 +00:00

ARC

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ARM

[MinGW] [ARM] Add stubs for potential automatic dllimported variables

2018-08-31 08:00:25 +00:00

AVR

[AVR] Set trackLivenessAfterRegAlloc

2018-06-11 14:46:48 +00:00

BPF

bpf: add missing RegState to notify MachineInstr verifier necessary register usage

2018-07-27 16:58:52 +00:00

Generic

[DWARF] Unclamp line table version on Darwin for v5 and later.

2018-08-08 21:16:50 +00:00

Hexagon

[Hexagon] Check validity of register class when generating bitsplit

2018-08-30 22:26:43 +00:00

Inputs

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Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[mips] Fix microMIPS unconditional branch offset handling

2018-08-29 14:54:01 +00:00

MIR

Consistently use MemoryLocation::UnknownSize to indicate unknown access size

2018-08-20 20:37:57 +00:00

MSP430

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

[PPC] Remove Darwin support from POWER backend.

2018-08-28 01:18:29 +00:00

RISCV

[RISCV] atomic_store_nn have a different layout to regular store

2018-08-27 07:08:18 +00:00

SPARC

[Sparc] Use ANDN instead of AND if constant can be encoded more efficiently

2018-08-30 14:05:26 +00:00

SystemZ

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Thumb

CodeGen: Make computeRegisterLiveness search forward first

2018-08-30 07:18:10 +00:00

Thumb2

[SelectionDAG] Improve the legalisation lowering of UMULO.

2018-08-16 18:39:39 +00:00

WebAssembly

[WebAssembly] Vector conversions

2018-08-30 21:43:51 +00:00

WinCFGuard

Rename the cfguard module flag to cfguardtable

2018-08-10 09:48:53 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[GlobalISel][X86] Add the support for G_FPTRUNC

2018-08-31 11:26:51 +00:00

XCore

[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

2018-07-15 16:27:07 +00:00