David Woodhouse 634295bcb6 Tests for mode switching ... 1. test that inlineasm works 2. test that relaxable instructions are re-encoded in the correct mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200351 91177308-0d34-0410-b5e6-96231b3b80d8		2014-01-28 23:13:30 +00:00
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AArch64	[AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SHUFFLE_VECTOR.	2014-01-27 02:53:54 +00:00
ARM	Tests for mode switching	2014-01-28 23:13:30 +00:00
CPP
Generic	Additional fix for 200201: due to dependence on bitwidth test was moved to X86 directory.	2014-01-27 09:43:10 +00:00
Hexagon
Inputs
Mips	[DAGCombiner] Teach how to fold sext/aext/zext of constant build vectors.	2014-01-27 18:45:30 +00:00
MSP430	Fix known typos	2014-01-24 17:20:08 +00:00
NVPTX	[NVPTX] Fix emitting aggregate parameters	2014-01-28 18:35:29 +00:00
PowerPC	Handle spilling the PPC GPRC_NOR0 register class	2014-01-28 05:32:58 +00:00
R600	R600/SI: Add pattern for truncating i32 to i1	2014-01-28 03:01:16 +00:00
SPARC	Fix the DWARF EH encodings for Sparc PIC code.	2014-01-28 02:52:26 +00:00
SystemZ	XFAIL test/CodeGen/SystemZ/alias-01.ll which requires CodeGen TBAA	2014-01-25 19:31:44 +00:00
Thumb	CodeGen: Stop treating vectors as aggregates	2014-01-21 22:46:46 +00:00
Thumb2	[Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForIT	2014-01-23 19:55:33 +00:00
X86	[X86] Add extra rules for combining vselect dag nodes into movsd.	2014-01-28 18:14:21 +00:00
XCore