Nate Begeman 6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector ... work. This change has no effect on generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8		2005-12-01 04:51:06 +00:00
..
SelectionDAG	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
AsmPrinter.cpp	Allow target to customize directive used to switch to arbitrary section in SwitchSection,	2005-11-21 08:25:09 +00:00
BranchFolding.cpp
ELFWriter.cpp	nuke blank line	2005-11-10 18:49:46 +00:00
IntrinsicLowering.cpp	continued readcyclecounter support	2005-11-11 16:47:30 +00:00
LiveInterval.cpp
LiveIntervalAnalysis.cpp	Fix some spello's pointed out by Gabor Greif	2005-10-26 18:41:41 +00:00
LiveVariables.cpp	Add section switching to common code generator code. Add a couple of	2005-11-21 07:06:27 +00:00
MachineBasicBlock.cpp
MachineCodeEmitter.cpp
MachineFunction.cpp
MachineInstr.cpp
Makefile
Passes.cpp	Alkis agrees that that iterative scan allocator isn't going to be worked on	2005-10-24 04:14:30 +00:00
PHIElimination.cpp
PhysRegTracker.h
PrologEpilogInserter.cpp	Always compute max align.	2005-11-06 17:43:20 +00:00
RegAllocLinearScan.cpp	I think I know what you meant here, but just to be safe I'll let you	2005-11-21 14:09:40 +00:00
RegAllocLocal.cpp	Nuke noop copies.	2005-11-09 18:22:42 +00:00
RegAllocSimple.cpp
TwoAddressInstructionPass.cpp	Fix some spello's pointed out by Gabor Greif	2005-10-26 18:41:41 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp
VirtRegMap.h