mirror of
https://github.com/RPCS3/llvm.git
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665814b6be
This is another part of the fix for Radar 8599955. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
414 lines
20 KiB
LLVM
414 lines
20 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vld1lanei8:
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;Check the (default) alignment value.
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;CHECK: vld1.8 {d16[3]}, [r0]
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%tmp1 = load <8 x i8>* %B
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%tmp2 = load i8* %A, align 8
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%tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vld1lanei16:
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;Check the alignment value. Max for this instruction is 16 bits:
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;CHECK: vld1.16 {d16[2]}, [r0, :16]
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%tmp1 = load <4 x i16>* %B
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%tmp2 = load i16* %A, align 8
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%tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vld1lanei32:
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;Check the alignment value. Max for this instruction is 16 bits:
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;CHECK: vld1.32 {d16[1]}, [r0, :32]
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%tmp1 = load <2 x i32>* %B
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%tmp2 = load i32* %A, align 8
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%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK: vld1laneQi8:
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;CHECK: vld1.8 {d17[1]}, [r0]
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%tmp1 = load <16 x i8>* %B
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%tmp2 = load i8* %A, align 8
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%tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vld1laneQi16:
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;CHECK: vld1.16 {d17[1]}, [r0, :16]
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%tmp1 = load <8 x i16>* %B
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%tmp2 = load i16* %A, align 8
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%tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vld1laneQi32:
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;CHECK: vld1.32 {d17[1]}, [r0, :32]
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%tmp1 = load <4 x i32>* %B
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%tmp2 = load i32* %A, align 8
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%tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3
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ret <4 x i32> %tmp3
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}
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%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
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%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
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define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vld2lanei8:
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;Check the alignment value. Max for this instruction is 16 bits:
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;CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16]
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%tmp1 = load <8 x i8>* %B
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%tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vld2lanei16:
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;Check the alignment value. Max for this instruction is 32 bits:
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;CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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%tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
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%tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1
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%tmp5 = add <4 x i16> %tmp3, %tmp4
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ret <4 x i16> %tmp5
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}
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define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vld2lanei32:
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;CHECK: vld2.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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%tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
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%tmp5 = add <2 x i32> %tmp3, %tmp4
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ret <2 x i32> %tmp5
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}
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define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK: vld2lanef:
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;CHECK: vld2.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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%tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1
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%tmp5 = fadd <2 x float> %tmp3, %tmp4
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ret <2 x float> %tmp5
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}
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define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vld2laneQi16:
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;Check the (default) alignment.
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;CHECK: vld2.16 {d17[1], d19[1]}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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%tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
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%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vld2laneQi32:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>* %B
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%tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
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%tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
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;CHECK: vld2laneQf:
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;CHECK: vld2.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>* %B
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%tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1
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%tmp5 = fadd <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
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declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
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declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
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declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8*, <2 x float>, <2 x float>, i32, i32) nounwind readonly
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declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
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declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
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declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind readonly
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%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
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define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vld3lanei8:
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;CHECK: vld3.8
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%tmp1 = load <8 x i8>* %B
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%tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
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%tmp6 = add <8 x i8> %tmp3, %tmp4
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%tmp7 = add <8 x i8> %tmp5, %tmp6
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ret <8 x i8> %tmp7
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}
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define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vld3lanei16:
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;Check the (default) alignment value. VLD3 does not support alignment.
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;CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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%tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
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%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 2
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%tmp6 = add <4 x i16> %tmp3, %tmp4
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%tmp7 = add <4 x i16> %tmp5, %tmp6
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ret <4 x i16> %tmp7
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}
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define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vld3lanei32:
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;CHECK: vld3.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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%tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 2
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%tmp6 = add <2 x i32> %tmp3, %tmp4
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%tmp7 = add <2 x i32> %tmp5, %tmp6
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ret <2 x i32> %tmp7
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}
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define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK: vld3lanef:
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;CHECK: vld3.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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%tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 2
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%tmp6 = fadd <2 x float> %tmp3, %tmp4
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%tmp7 = fadd <2 x float> %tmp5, %tmp6
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ret <2 x float> %tmp7
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}
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define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vld3laneQi16:
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;Check the (default) alignment value. VLD3 does not support alignment.
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;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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%tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
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%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
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%tmp6 = add <8 x i16> %tmp3, %tmp4
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%tmp7 = add <8 x i16> %tmp5, %tmp6
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ret <8 x i16> %tmp7
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}
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define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vld3laneQi32:
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;CHECK: vld3.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>* %B
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%tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3, i32 1)
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%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2
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%tmp6 = add <4 x i32> %tmp3, %tmp4
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%tmp7 = add <4 x i32> %tmp5, %tmp6
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ret <4 x i32> %tmp7
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}
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define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
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;CHECK: vld3laneQf:
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;CHECK: vld3.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>* %B
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%tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2
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%tmp6 = fadd <4 x float> %tmp3, %tmp4
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%tmp7 = fadd <4 x float> %tmp5, %tmp6
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ret <4 x float> %tmp7
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}
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declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
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declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
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declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
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declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly
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declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
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declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
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declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
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define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vld4lanei8:
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;Check the alignment value. Max for this instruction is 32 bits:
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;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
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%tmp1 = load <8 x i8>* %B
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%tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
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%tmp7 = add <8 x i8> %tmp3, %tmp4
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%tmp8 = add <8 x i8> %tmp5, %tmp6
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%tmp9 = add <8 x i8> %tmp7, %tmp8
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ret <8 x i8> %tmp9
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}
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define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vld4lanei16:
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;CHECK: vld4.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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%tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 3
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%tmp7 = add <4 x i16> %tmp3, %tmp4
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%tmp8 = add <4 x i16> %tmp5, %tmp6
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%tmp9 = add <4 x i16> %tmp7, %tmp8
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ret <4 x i16> %tmp9
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}
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define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vld4lanei32:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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%tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
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%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 3
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%tmp7 = add <2 x i32> %tmp3, %tmp4
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%tmp8 = add <2 x i32> %tmp5, %tmp6
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%tmp9 = add <2 x i32> %tmp7, %tmp8
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ret <2 x i32> %tmp9
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}
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define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK: vld4lanef:
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;CHECK: vld4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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%tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 3
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%tmp7 = fadd <2 x float> %tmp3, %tmp4
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%tmp8 = fadd <2 x float> %tmp5, %tmp6
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%tmp9 = fadd <2 x float> %tmp7, %tmp8
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ret <2 x float> %tmp9
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}
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define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vld4laneQi16:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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%tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16)
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%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 3
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%tmp7 = add <8 x i16> %tmp3, %tmp4
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%tmp8 = add <8 x i16> %tmp5, %tmp6
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%tmp9 = add <8 x i16> %tmp7, %tmp8
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ret <8 x i16> %tmp9
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}
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define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vld4laneQi32:
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;Check the (default) alignment.
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;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>* %B
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%tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
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%tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 3
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%tmp7 = add <4 x i32> %tmp3, %tmp4
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%tmp8 = add <4 x i32> %tmp5, %tmp6
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%tmp9 = add <4 x i32> %tmp7, %tmp8
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ret <4 x i32> %tmp9
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}
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define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
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;CHECK: vld4laneQf:
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;CHECK: vld4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>* %B
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%tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
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%tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 3
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%tmp7 = fadd <4 x float> %tmp3, %tmp4
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%tmp8 = fadd <4 x float> %tmp5, %tmp6
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%tmp9 = fadd <4 x float> %tmp7, %tmp8
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ret <4 x float> %tmp9
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}
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declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
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declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
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declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
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declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly
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declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
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declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
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declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
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