Evan Cheng 676b2dfd27 Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-05 22:15:40 +00:00
..
Analysis	Use the SCEVAddRecExpr::getPostIncExpr utility function instead	2010-05-04 01:12:27 +00:00
Archive	silence a warning, patch by "mike".	2010-04-25 04:44:26 +00:00
AsmParser	Remove the API compatibility layer which converted add, sub, and mul	2010-05-03 22:44:19 +00:00
Bitcode	Revert 101465, it broke internal OpenGL testing.	2010-04-16 23:37:20 +00:00
CodeGen	Move REG_SEQUENCE removal to 2addr pass.	2010-05-05 18:45:40 +00:00
CompilerDriver
ExecutionEngine	Remove the -enable-sjlj-eh option, which doesn't do anything.	2010-05-02 15:36:26 +00:00
Linker
MC	MC/Mach-O: Mark absolute variable's appropriately, and add Mach-O support for	2010-05-05 19:01:05 +00:00
Support	Implement rdar://7415680 - Twine integer support lacks greatness	2010-05-05 18:40:33 +00:00
System	This doesn't need SmallVector.h anymore.	2010-04-19 17:51:31 +00:00
Target	Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.	2010-05-05 22:15:40 +00:00
Transforms	Use the right version of "append" to combine two SmallVectors.	2010-05-05 20:44:15 +00:00
VMCore	Fix a problem exposed by my previous commit and noticed by a release-asserts	2010-05-04 14:25:42 +00:00
Makefile