llvm/test/CodeGen/Thumb2/thumb2-orr2.ll
Joerg Sonnenberger aca2998f14 Enabling thumb2 mode used to force support for armv6t2. Replace this
with a temporary assertion and adjust the various test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-13 11:16:00 +00:00

43 lines
838 B
LLVM

; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 | FileCheck %s
; 0x000000bb = 187
define i32 @f1(i32 %a) {
%tmp2 = or i32 %a, 187
ret i32 %tmp2
}
; CHECK-LABEL: f1:
; CHECK: orr r0, r0, #187
; 0x00aa00aa = 11141290
define i32 @f2(i32 %a) {
%tmp2 = or i32 %a, 11141290
ret i32 %tmp2
}
; CHECK-LABEL: f2:
; CHECK: orr r0, r0, #11141290
; 0xcc00cc00 = 3422604288
define i32 @f3(i32 %a) {
%tmp2 = or i32 %a, 3422604288
ret i32 %tmp2
}
; CHECK-LABEL: f3:
; CHECK: orr r0, r0, #-872363008
; 0x44444444 = 1145324612
define i32 @f4(i32 %a) {
%tmp2 = or i32 %a, 1145324612
ret i32 %tmp2
}
; CHECK-LABEL: f4:
; CHECK: orr r0, r0, #1145324612
; 0x00110000 = 1114112
define i32 @f5(i32 %a) {
%tmp2 = or i32 %a, 1114112
ret i32 %tmp2
}
; CHECK-LABEL: f5:
; CHECK: orr r0, r0, #1114112