llvm/test/TableGen/arithmetic.td
Nicolai Haehnle 8ed1fd468a TableGen: Type-check BinOps
Additionally, allow more than two operands to !con, !add, !and, !or
in the same way as is already allowed for !listconcat and !strconcat.

Change-Id: I9659411f554201b90cd8ed7c7e004d381a66fa93

Differential revision: https://reviews.llvm.org/D44112

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327494 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-14 11:00:43 +00:00

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708 B
TableGen

// RUN: llvm-tblgen %s | FileCheck %s
// XFAIL: vg_leak
// CHECK: --- Defs ---
// CHECK: def A0 {
// CHECK: bits<8> add = { 0, 1, 0, 0, 0, 0, 0, 0 };
// CHECK: bits<8> and = { 0, 0, 0, 0, 0, 0, 0, 1 };
// CHECK: bits<8> or = { 0, 0, 1, 1, 1, 1, 1, 1 };
// CHECK: bits<8> srl = { 0, 0, 0, 1, 1, 1, 1, 1 };
// CHECK: bits<8> sra = { 0, 0, 0, 1, 1, 1, 1, 1 };
// CHECK: bits<8> shl = { 0, 1, 1, 1, 1, 1, 1, 0 };
// CHECK: }
class A<bits<8> a, bits<2> b> {
// Operands of different bits types are allowed.
bits<8> add = !add(a, b);
bits<8> and = !and(a, b);
bits<8> or = !or(a, b);
bits<8> srl = !srl(a, b);
bits<8> sra = !sra(a, b);
bits<8> shl = !shl(a, b);
}
def A0 : A<63, 1>;