mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-05 02:07:16 +00:00
7bf0a7f962
Summary: We will use this in the AMDGPU backend in a subsequent patch in the stack to lookup target-specific per-intrinsic information. The generic CodeGenIntrinsic machinery is used to ensure that, even though we don't calculate actual enum values here, we do get the intrinsics in the right order for the binary search index. Change-Id: If61cd5587963a4c5a1cc53df1e59c5e4dec1f9dc Reviewers: arsenm, rampitec, b-sumner Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D44935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328937 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.5 KiB
TableGen
86 lines
2.5 KiB
TableGen
// RUN: llvm-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
|
|
// XFAIL: vg_leak
|
|
|
|
include "llvm/TableGen/SearchableTable.td"
|
|
|
|
class IntrinsicProperty;
|
|
class SDNodeProperty;
|
|
|
|
class ValueType<int size, int value> {
|
|
string Namespace = "MVT";
|
|
int Size = size;
|
|
int Value = value;
|
|
}
|
|
|
|
class LLVMType<ValueType vt> {
|
|
ValueType VT = vt;
|
|
}
|
|
|
|
class Intrinsic<list<LLVMType> param_types = []> {
|
|
string LLVMName = "";
|
|
bit isTarget = 0;
|
|
string TargetPrefix = "";
|
|
list<LLVMType> RetTypes = [];
|
|
list<LLVMType> ParamTypes = param_types;
|
|
list<IntrinsicProperty> IntrProperties = [];
|
|
list<SDNodeProperty> Properties = [];
|
|
}
|
|
|
|
def iAny : ValueType<0, 253>;
|
|
def llvm_anyint_ty : LLVMType<iAny>;
|
|
|
|
def int_abc : Intrinsic<[llvm_anyint_ty]>;
|
|
def int_xyz : Intrinsic<[llvm_anyint_ty]>;
|
|
|
|
let isTarget = 1, TargetPrefix = "gtarget" in {
|
|
def int_gtarget_def : Intrinsic<[llvm_anyint_ty]>;
|
|
def int_gtarget_defg : Intrinsic<[llvm_anyint_ty]>;
|
|
def int_gtarget_uvw : Intrinsic<[llvm_anyint_ty]>;
|
|
}
|
|
|
|
let isTarget = 1, TargetPrefix = "ftarget" in {
|
|
def int_ftarget_ghi : Intrinsic<[llvm_anyint_ty]>;
|
|
def int_ftarget_ghi_x : Intrinsic<[llvm_anyint_ty]>;
|
|
def int_ftarget_rst : Intrinsic<[llvm_anyint_ty]>;
|
|
}
|
|
|
|
class Table<Intrinsic intr, int payload> : SearchableTable {
|
|
let SearchableFields = ["Intr"];
|
|
let EnumNameField = ?;
|
|
|
|
Intrinsic Intr = !cast<Intrinsic>(intr);
|
|
bits<16> Payload = payload;
|
|
}
|
|
|
|
// CHECK-LABEL: TablesList[] = {
|
|
// CHECK-DAG: { Intrinsic::abc, 0x0},
|
|
// CHECK-DAG: { Intrinsic::xyz, 0x1},
|
|
// CHECK-DAG: { Intrinsic::gtarget_def, 0x10},
|
|
// CHECK-DAG: { Intrinsic::gtarget_defg, 0x11},
|
|
// CHECK-DAG: { Intrinsic::gtarget_uvw, 0x12},
|
|
// CHECK-DAG: { Intrinsic::ftarget_ghi, 0x20},
|
|
// CHECK-DAG: { Intrinsic::ftarget_ghi_x, 0x21},
|
|
// CHECK-DAG: { Intrinsic::ftarget_rst, 0x22},
|
|
|
|
// Check that the index is in the correct order, consistent with the ordering
|
|
// of enums: alphabetically, but target intrinsics after generic intrinsics
|
|
//
|
|
// CHECK-LABEL: TablesByIntr[] = {
|
|
// CHECK-NEXT: Intrinsic::abc
|
|
// CHECK-NEXT: Intrinsic::xyz
|
|
// CHECK-NEXT: Intrinsic::ftarget_ghi
|
|
// CHECK-NEXT: Intrinsic::ftarget_ghi_x
|
|
// CHECK-NEXT: Intrinsic::ftarget_rst
|
|
// CHECK-NEXT: Intrinsic::gtarget_def
|
|
// CHECK-NEXT: Intrinsic::gtarget_defg
|
|
// CHECK-NEXT: Intrinsic::gtarget_uvw
|
|
|
|
def : Table<int_abc, 0x0>;
|
|
def : Table<int_xyz, 0x1>;
|
|
def : Table<int_gtarget_def, 0x10>;
|
|
def : Table<int_gtarget_defg, 0x11>;
|
|
def : Table<int_gtarget_uvw, 0x12>;
|
|
def : Table<int_ftarget_ghi, 0x20>;
|
|
def : Table<int_ftarget_ghi_x, 0x21>;
|
|
def : Table<int_ftarget_rst, 0x22>;
|