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Alpha
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Add bswap, rotl, and rotr nodes
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2006-01-11 21:21:00 +00:00 |
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CBackend
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yet more C++ standards-compliance stuff.
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2005-12-27 10:40:34 +00:00 |
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IA64
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Add bswap, rotl, and rotr nodes
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2006-01-11 21:21:00 +00:00 |
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PowerPC
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Add bswap, rotl, and rotr nodes
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2006-01-11 21:21:00 +00:00 |
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Skeleton
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Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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2005-12-01 04:51:06 +00:00 |
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Sparc
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Add bswap, rotl, and rotr nodes
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2006-01-11 21:21:00 +00:00 |
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SparcV8
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Add bswap, rotl, and rotr nodes
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2006-01-11 21:21:00 +00:00 |
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SparcV9
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Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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2005-12-01 04:51:06 +00:00 |
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X86
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Support for MEMCPY and MEMSET.
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2006-01-11 22:15:48 +00:00 |
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Makefile
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DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now
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2005-10-24 02:26:13 +00:00 |
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MRegisterInfo.cpp
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Rename MRegisterDesc -> TargetRegisterDesc for consistency
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2005-09-30 17:49:27 +00:00 |
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SubtargetFeature.cpp
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Preparation of supporting scheduling info. Need to find info based on selected
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2005-10-25 15:15:28 +00:00 |
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Target.td
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New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
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2006-01-09 18:28:21 +00:00 |
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TargetData.cpp
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TargetFrameInfo.cpp
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TargetInstrInfo.cpp
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TargetMachine.cpp
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Remove the X86 and PowerPC Simple instruction selectors; their time has
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2005-08-18 23:53:15 +00:00 |
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TargetMachineRegistry.cpp
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1. Use SubtargetFeatures in llc/lli.
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2005-09-01 21:38:21 +00:00 |
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TargetSchedInfo.cpp
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TargetSchedule.td
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add a marker
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2005-10-23 22:07:20 +00:00 |
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TargetSelectionDAG.td
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Add bswap, rotl, and rotr nodes
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2006-01-11 21:21:00 +00:00 |
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TargetSubtarget.cpp
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