Daniel Sanders 4d7894c6d8 [globalisel][tablegen] Add support for multi-insn emission ... The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317117 91177308-0d34-0410-b5e6-96231b3b80d8		2017-11-01 19:57:57 +00:00
..
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
AnonDefinitionOnDemand.td
AsmPredicateCondsEmission.td	Use std::bitset for SubtargetFeatures.	2015-05-26 10:47:10 +00:00
AsmVariant.td	[TableGen] Add a proper namespace to an Instruction in an AsmMatcher test. This is required after r307358.	2017-07-07 05:50:45 +00:00
BitOffsetDecoder.td	Update test case to match minor formatting change introduced in r218563.	2014-09-27 05:36:53 +00:00
BitsInit.td	Tablegen fixes for new syntax when initializing bits from variables.	2014-08-29 19:41:04 +00:00
BitsInitOverflow.td
cast-list-initializer.td	TableGen: Support folding casts from bits to int	2015-07-31 01:12:06 +00:00
cast.td
ClassInstanceValue.td	[TableGen] Fully resolve class-instance values before defs in multiclasses	2014-09-16 17:14:13 +00:00
ConcatenatedSubregs.td	Address r311914 review comments	2017-08-28 20:11:27 +00:00
CStyleComment.td
Dag.td
defmclass.td
DefmInherit.td
DefmInsideMultiClass.td
DuplicateFieldValues.td	[tablegen] Delete duplicates from a vector without skipping elements	2016-12-01 19:38:50 +00:00
eq.td
eqbit.td
FieldAccess.td
foreach.td
ForeachList.td	llvm/test/TableGen/*Foreach*.td: Remove XFAIL:vg_leak. They have not been failing since r215176.	2014-08-12 14:06:21 +00:00
ForeachLoop.td	llvm/test/TableGen/*Foreach*.td: Remove XFAIL:vg_leak. They have not been failing since r215176.	2014-08-12 14:06:21 +00:00
ForwardRef.td
GeneralList.td	test/TableGen: Remove XFAIL:vg_leak out of 3 tests corresponding to r208293.	2014-05-09 08:18:33 +00:00
GlobalISelEmitter.td	[globalisel][tablegen] Add support for multi-insn emission	2017-11-01 19:57:57 +00:00
HwModeSelect.td	TableGen support for parameterized register class information	2017-09-14 16:56:21 +00:00
if-empty-list-arg.td	Fix error in tablegen when either operand of !if is an empty list.	2014-06-10 20:10:08 +00:00
if.td	Change BitsInit to inherit from TypedInit.	2014-08-07 05:47:04 +00:00
ifbit.td	Update BitRecTy::convertValue to allow if expressions with bit values on both sides of the if	2014-08-07 05:47:10 +00:00
Include.inc
Include.td
IntBitInit.td
intrinsic-long-name.td	[MVT][SVE] Scalable vector MVTs (2/3)	2017-04-20 13:36:58 +00:00
intrinsic-struct.td	[TableGen] Allow intrinsics to have up to 8 return values.	2017-10-12 17:40:00 +00:00
intrinsic-varargs.td	[MVT] add v1i1 MVT	2017-05-18 11:29:41 +00:00
LazyChange.td
LetInsideMultiClasses.td
lisp.td	test/TableGen: Remove XFAIL:vg_leak out of 3 tests corresponding to r208293.	2014-05-09 08:18:33 +00:00
list-element-bitref.td	Change BitsInit to inherit from TypedInit.	2014-08-07 05:47:04 +00:00
ListArgs.td
ListArgsSimple.td
listconcat.td	test/TableGen: Remove XFAIL:vg_leak out of 3 tests corresponding to r208293.	2014-05-09 08:18:33 +00:00
ListConversion.td
ListManip.td
ListOfList.td
ListSlices.td
lit.local.cfg
LoLoL.td
math.td	TableGen: Add operator !or	2016-11-15 06:49:28 +00:00
MultiClass.td
MultiClassDefName.td	[TableGen] Resolve complex def names inside multiclasses	2015-05-21 04:32:56 +00:00
MultiClassInherit.td
MultiPat.td
nested-comment.td
NestedForeach.td	llvm/test/TableGen/*Foreach*.td: Remove XFAIL:vg_leak. They have not been failing since r215176.	2014-08-12 14:06:21 +00:00
Paste.td
pr8330.td
RegisterBankEmitter.td	TableGen: Fix infinite recursion in RegisterBankEmitter	2017-01-30 15:07:01 +00:00
RegisterEncoder.td	[TableGen] Add EncoderMethod to RegisterOperand	2017-05-15 10:13:07 +00:00
SetTheory.td
SiblingForeach.td	llvm/test/TableGen/*Foreach*.td: Remove XFAIL:vg_leak. They have not been failing since r215176.	2014-08-12 14:06:21 +00:00
Slice.td
strconcat.td
String.td
subst2.td
subst.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td
TemplateArgRename.td
Tree.td
TreeNames.td
trydecode-emission2.td	tests: accept different TargetOpcode values.	2016-07-07 17:51:42 +00:00
trydecode-emission3.td	tests: accept different TargetOpcode values.	2016-07-07 17:51:42 +00:00
trydecode-emission.td	tests: accept different TargetOpcode values.	2016-07-07 17:51:42 +00:00
TwoLevelName.td	Add test cases that will show the bug that was fixed in r256725.	2016-01-13 07:53:11 +00:00
UnsetBitInit.td
UnterminatedComment.td	Make shell redirection construct portable	2017-07-12 13:24:46 +00:00
usevalname.td
ValidIdentifiers.td