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llvm
/
lib
/
Target
/
Hexagon
History
Chad Rosier
5b3fca50a0
The getRegForInlineAsmConstraint function should only accept MVT value types.
...
git-svn-id:
https://llvm.org/svn/llvm-project/llvm/trunk@184642
91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-22 18:37:38 +00:00
..
InstPrinter
MCTargetDesc
TargetInfo
CMakeLists.txt
Hexagon.h
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
2013-06-19 21:36:55 +00:00
Hexagon.td
HexagonAsmPrinter.cpp
HexagonAsmPrinter.h
HexagonCallingConv.td
HexagonCallingConvLower.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 06:19:56 +00:00
HexagonCallingConvLower.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 06:19:56 +00:00
HexagonCFGOptimizer.cpp
HexagonCopyToCombine.cpp
Hexagon: Typo fix.
2013-05-28 19:01:45 +00:00
HexagonExpandPredSpillCode.cpp
HexagonFixupHwLoops.cpp
HexagonFrameLowering.cpp
HexagonFrameLowering.h
HexagonHardwareLoops.cpp
HexagonInstrFormats.td
HexagonInstrFormatsV4.td
HexagonInstrInfo.cpp
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
2013-06-16 20:34:27 +00:00
HexagonInstrInfo.h
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
2013-06-16 20:34:27 +00:00
HexagonInstrInfo.td
HexagonInstrInfoV3.td
HexagonInstrInfoV4.td
HexagonInstrInfoV5.td
HexagonIntrinsics.td
HexagonIntrinsicsDerived.td
HexagonIntrinsicsV3.td
HexagonIntrinsicsV4.td
HexagonIntrinsicsV5.td
HexagonISelDAGToDAG.cpp
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
2013-06-19 21:36:55 +00:00
HexagonISelLowering.cpp
The getRegForInlineAsmConstraint function should only accept MVT value types.
2013-06-22 18:37:38 +00:00
HexagonISelLowering.h
The getRegForInlineAsmConstraint function should only accept MVT value types.
2013-06-22 18:37:38 +00:00
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp
Machine Model: Add MicroOpBufferSize and resource BufferSize.
2013-06-15 04:49:57 +00:00
HexagonMachineScheduler.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 06:19:56 +00:00
HexagonMCInstLower.cpp
HexagonNewValueJump.cpp
HexagonOperands.td
HexagonPeephole.cpp
HexagonRegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 06:19:56 +00:00
HexagonRegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 06:19:56 +00:00
HexagonRegisterInfo.td
Make SubRegIndex size mandatory, following r183020.
2013-05-31 23:45:26 +00:00
HexagonRemoveSZExtArgs.cpp
HexagonSchedule.td
HexagonScheduleV4.td
HexagonSelectCCInfo.td
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitConst32AndConst64.cpp
HexagonSplitTFRCondSets.cpp
HexagonSubtarget.cpp
HexagonSubtarget.h
HexagonTargetMachine.cpp
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
2013-06-19 21:36:55 +00:00
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp
HexagonTargetObjectFile.h
HexagonVarargsCallingConvention.h
HexagonVLIWPacketizer.cpp
LLVMBuild.txt
Makefile