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6c868a4c17
modifications for 1 LLVM BB --> many MBBs). Fix store operand order: make it always be Base, Offset, SrcReg (think "[ Base + Offset ] = SrcReg"). Rewrite visitBranchInst() to be even dumber (but working) -- give up on the branch fallthrough trick, for the time being. Make visitSetCondInst() work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14208 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
DelaySlotFiller.cpp | ||
InstSelectSimple.cpp | ||
Makefile | ||
README.txt | ||
SparcV8.h | ||
SparcV8.td | ||
SparcV8AsmPrinter.cpp | ||
SparcV8CodeEmitter.cpp | ||
SparcV8InstrInfo_F2.td | ||
SparcV8InstrInfo_F3.td | ||
SparcV8InstrInfo.cpp | ||
SparcV8InstrInfo.h | ||
SparcV8InstrInfo.td | ||
SparcV8ISelSimple.cpp | ||
SparcV8JITInfo.h | ||
SparcV8RegisterInfo.cpp | ||
SparcV8RegisterInfo.h | ||
SparcV8RegisterInfo.td | ||
SparcV8TargetMachine.cpp | ||
SparcV8TargetMachine.h |
SparcV8 backend skeleton ------------------------ This directory will house a 32-bit SPARC V8 backend employing a expander-based instruction selector. Watch this space for more news coming soon! $Date$