JF Bastien 6d2f2ee4ab WebAssembly: textual emission uses expected opcode names ...

Summary: WebAssembly's tablegen instructions have the names WebAssembly expects, but by LLVM convention they're uppercase and suffixed with their type after an underscore. Leave the C++ code that way, but print outt he names WebAssembly expects (lowercase, no type). We could teach tablegen to do this later, maybe by using `!cast<string>(node)` in the .td files.

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D11776

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244305 91177308-0d34-0410-b5e6-96231b3b80d8

2015-08-07 01:57:03 +00:00

..

AArch64

[AArch64][FastISel] Always use AND before checking the branch flag.

2015-08-06 22:44:15 +00:00

AMDGPU

AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CI

2015-08-06 19:28:38 +00:00

ARM

Fix possible infinite loop in shrink wrapping when searching for save/restore

2015-08-06 19:01:57 +00:00

BPF

[bpf] rename triple names bpf_be -> bpfeb

2015-06-05 16:11:14 +00:00

CPP

[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction

2015-04-16 23:24:18 +00:00

Generic

Update test suite to make "ninja check" succeed without native backend builtin

2015-08-04 06:32:54 +00:00

Hexagon

DI: Disallow uniquable DICompileUnits

2015-08-03 17:26:41 +00:00

Inputs

DI: Disallow uniquable DICompileUnits

2015-08-03 17:26:41 +00:00

Mips

Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.

2015-08-04 14:26:35 +00:00

MIR

MIR Serialization: Fix serialization of unnamed IR block references.

2015-08-06 23:57:04 +00:00

MSP430

[opaque pointer type] Add textual IR support for explicit type parameter to gep operator

2015-03-13 18:20:45 +00:00

NVPTX

[NVPTX] Use LDG for pointer induction variables.

2015-08-05 23:11:57 +00:00

PowerPC

[MachineCombiner] Don't use the opcode-only form of computeInstrLatency

2015-08-05 07:45:28 +00:00

SPARC

[SPARC] Cleanup handling of the Y/ASR registers.

2015-07-08 16:25:12 +00:00

SystemZ

[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load

2015-05-05 19:34:10 +00:00

Thumb

DI: Disallow uniquable DICompileUnits

2015-08-03 17:26:41 +00:00

Thumb2

ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2

2015-07-21 00:18:59 +00:00

WebAssembly

WebAssembly: textual emission uses expected opcode names

2015-08-07 01:57:03 +00:00

WinEH

[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name

2015-07-13 17:55:14 +00:00

X86

Fix possible infinite loop in shrink wrapping when searching for save/restore

2015-08-06 19:01:57 +00:00

XCore

DI: Disallow uniquable DICompileUnits

2015-08-03 17:26:41 +00:00