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ffc49cbea4
The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181620 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
917 B
ArmAsm
34 lines
917 B
ArmAsm
// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
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// RUN: FileCheck --check-prefix=64 < %t.err %s
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// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
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// RUN: FileCheck --check-prefix=32 < %t.err %s
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// rdar://8204588
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// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
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cmp $0, 0(%eax)
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// 32: error: register %rax is only available in 64-bit mode
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addl $0, 0(%rax)
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// 32: test.s:8:2: error: invalid instruction mnemonic 'movi'
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# 8 "test.s"
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movi $8,%eax
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movl 0(%rax), 0(%edx) // error: invalid operand for instruction
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// 32: error: instruction requires: 64-bit mode
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sysexitq
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// rdar://10710167
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// 64: error: expected scale expression
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lea (%rsp, %rbp, $4), %rax
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// rdar://10423777
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// 64: error: index register is 32-bit, but base register is 64-bit
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movq (%rsi,%ecx),%xmm0
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// 32: error: invalid operand for instruction
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outb al, 4
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