mirror of
https://github.com/RPCS3/llvm.git
synced 2025-01-09 21:50:50 +00:00
70c9be77f7
The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214498 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
---|---|---|
.. | ||
AArch64 | ||
ARM | ||
AsmParser | ||
COFF | ||
Disassembler | ||
ELF | ||
MachO | ||
Markup | ||
Mips | ||
PowerPC | ||
Sparc | ||
SystemZ | ||
X86 |