Tim Northover 5b1552548a X86: allow registers 8-15 in test ...

This test was failing on some hosts when an unexpected register was used for a
variable. This just extends the regexp to allow the new x86-64 registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182929 91177308-0d34-0410-b5e6-96231b3b80d8

2013-05-30 13:56:32 +00:00

..

AArch64

Change how we iterate over relocations on ELF.

2013-05-30 03:05:14 +00:00

ARM

Change how we iterate over relocations on ELF.

2013-05-30 03:05:14 +00:00

CPP

test commit: remove blank line.

2013-03-14 05:43:59 +00:00

Generic

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

2013-05-21 14:37:16 +00:00

Hexagon

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

Inputs

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

MBlaze

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00

Mips

Track IR ordering of SelectionDAG nodes 4/4.

2013-05-25 03:26:51 +00:00

MSP430

DAGCombiner: Simplify inverted bit tests

2013-05-08 06:44:42 +00:00

NVPTX

[NVPTX] Fix case where a sext load of an i1 type may produce an

2013-05-30 12:22:39 +00:00

PowerPC

Change how we iterate over relocations on ELF.

2013-05-30 03:05:14 +00:00

R600

R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg

2013-05-23 18:26:42 +00:00

SI

Add R600 backend

2012-12-11 21:25:42 +00:00

SPARC

[Sparc] Add support for leaf functions in sparc backend.

2013-05-29 04:46:31 +00:00

SystemZ

[SystemZ] Enable unaligned accesses

2013-05-30 09:45:42 +00:00

Thumb

LocalStackSlotAllocation improvements

2013-04-30 20:04:37 +00:00

Thumb2

Fix ARM FastISel tests, as a first step to enabling ARM FastISel

2013-05-14 16:26:38 +00:00

X86

X86: allow registers 8-15 in test

2013-05-30 13:56:32 +00:00

XCore

[XCore] Fix handling of functions where only the LR is spilled.

2013-05-09 16:43:42 +00:00