David Woodhouse 7360e8caa3 [x86] Fix 16-bit handling of OpSize bit ...

When disassembling in 16-bit mode the meaning of the OpSize bit is
inverted. Instructions found in the IC_OPSIZE context will actually
*not* have the 0x66 prefix, and instructions in the IC context will
have the 0x66 prefix. Make use of the existing special-case handling
for the 0x66 prefix being in the wrong place, to cope with this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199650 91177308-0d34-0410-b5e6-96231b3b80d8

2014-01-20 12:02:35 +00:00

..

AArch64

[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.

2013-11-29 01:29:16 +00:00

ARM

ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions

2014-01-12 04:36:01 +00:00

Mips

LL and SC decoder method fix.

2014-01-15 13:17:33 +00:00

PowerPC

Add a disassembler to the PowerPC backend

2013-12-19 16:13:01 +00:00

Sparc

[Sparc] Add support for parsing floating point instructions.

2014-01-12 04:48:54 +00:00

SystemZ

[SystemZ] Add MC support for interlocked-access 1 instructions

2013-12-24 15:14:05 +00:00

X86

[x86] Fix 16-bit handling of OpSize bit

2014-01-20 12:02:35 +00:00

XCore

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00