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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212896 91177308-0d34-0410-b5e6-96231b3b80d8
553 lines
16 KiB
C++
553 lines
16 KiB
C++
//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This pass lowers the pseudo control flow instructions to real
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/// machine instructions.
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///
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/// All control flow is handled using predicated instructions and
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/// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
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/// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
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/// by writting to the 64-bit EXEC register (each bit corresponds to a
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/// single vector ALU). Typically, for predicates, a vector ALU will write
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/// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
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/// Vector ALU) and then the ScalarALU will AND the VCC register with the
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/// EXEC to update the predicates.
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///
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/// For example:
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/// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
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/// %SGPR0 = SI_IF %VCC
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/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
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/// %SGPR0 = SI_ELSE %SGPR0
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/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
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/// SI_END_CF %SGPR0
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///
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/// becomes:
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///
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/// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
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/// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
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/// S_CBRANCH_EXECZ label0 // This instruction is an optional
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/// // optimization which allows us to
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/// // branch if all the bits of
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/// // EXEC are zero.
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/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
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///
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/// label0:
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/// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
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/// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
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/// S_BRANCH_EXECZ label1 // Use our branch optimization
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/// // instruction again.
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/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
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/// label1:
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/// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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using namespace llvm;
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namespace {
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class SILowerControlFlowPass : public MachineFunctionPass {
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private:
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static const unsigned SkipThreshold = 12;
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static char ID;
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const SIRegisterInfo *TRI;
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const SIInstrInfo *TII;
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bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
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void Skip(MachineInstr &From, MachineOperand &To);
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void SkipIfDead(MachineInstr &MI);
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void If(MachineInstr &MI);
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void Else(MachineInstr &MI);
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void Break(MachineInstr &MI);
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void IfBreak(MachineInstr &MI);
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void ElseBreak(MachineInstr &MI);
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void Loop(MachineInstr &MI);
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void EndCf(MachineInstr &MI);
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void Kill(MachineInstr &MI);
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void Branch(MachineInstr &MI);
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void InitM0ForLDS(MachineBasicBlock::iterator MI);
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void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
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void IndirectSrc(MachineInstr &MI);
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void IndirectDst(MachineInstr &MI);
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public:
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SILowerControlFlowPass(TargetMachine &tm) :
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MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { }
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI Lower control flow instructions";
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}
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};
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} // End anonymous namespace
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char SILowerControlFlowPass::ID = 0;
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FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
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return new SILowerControlFlowPass(tm);
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}
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bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
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MachineBasicBlock *To) {
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unsigned NumInstr = 0;
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for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
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MBB = *MBB->succ_begin()) {
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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NumInstr < SkipThreshold && I != E; ++I) {
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if (I->isBundle() || !I->isBundled())
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if (++NumInstr >= SkipThreshold)
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return true;
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}
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}
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return false;
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}
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void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
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if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
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return;
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DebugLoc DL = From.getDebugLoc();
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BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
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.addOperand(To)
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.addReg(AMDGPU::EXEC);
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}
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void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->getShaderType() !=
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ShaderType::PIXEL ||
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!shouldSkip(&MBB, &MBB.getParent()->back()))
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return;
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MachineBasicBlock::iterator Insert = &MI;
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++Insert;
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// If the exec mask is non-zero, skip the next two instructions
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
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.addImm(3)
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.addReg(AMDGPU::EXEC);
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// Exec mask is zero: Export to NULL target...
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
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.addImm(0)
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.addImm(0x09) // V_008DFC_SQ_EXP_NULL
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.addImm(0)
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.addImm(1)
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.addImm(1)
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.addReg(AMDGPU::VGPR0)
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.addReg(AMDGPU::VGPR0)
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.addReg(AMDGPU::VGPR0)
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.addReg(AMDGPU::VGPR0);
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// ... and terminate wavefront
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
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}
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void SILowerControlFlowPass::If(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Reg = MI.getOperand(0).getReg();
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unsigned Vcc = MI.getOperand(1).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
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.addReg(Vcc);
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
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.addReg(AMDGPU::EXEC)
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.addReg(Reg);
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Skip(MI, MI.getOperand(2));
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::Else(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Src = MI.getOperand(1).getReg();
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BuildMI(MBB, MBB.getFirstNonPHI(), DL,
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TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
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.addReg(Src); // Saved EXEC
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(Dst);
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Skip(MI, MI.getOperand(2));
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::Break(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Src = MI.getOperand(1).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
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.addReg(AMDGPU::EXEC)
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.addReg(Src);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Vcc = MI.getOperand(1).getReg();
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unsigned Src = MI.getOperand(2).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
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.addReg(Vcc)
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.addReg(Src);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Saved = MI.getOperand(1).getReg();
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unsigned Src = MI.getOperand(2).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
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.addReg(Saved)
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.addReg(Src);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::Loop(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Src = MI.getOperand(0).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(Src);
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
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.addOperand(MI.getOperand(1))
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.addReg(AMDGPU::EXEC);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Reg = MI.getOperand(0).getReg();
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BuildMI(MBB, MBB.getFirstNonPHI(), DL,
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TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(Reg);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::Branch(MachineInstr &MI) {
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if (MI.getOperand(0).getMBB() == MI.getParent()->getNextNode())
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MI.eraseFromParent();
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// If these aren't equal, this is probably an infinite loop.
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}
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void SILowerControlFlowPass::Kill(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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const MachineOperand &Op = MI.getOperand(0);
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#ifndef NDEBUG
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const SIMachineFunctionInfo *MFI
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= MBB.getParent()->getInfo<SIMachineFunctionInfo>();
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// Kill is only allowed in pixel / geometry shaders.
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assert(MFI->getShaderType() == ShaderType::PIXEL ||
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MFI->getShaderType() == ShaderType::GEOMETRY);
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#endif
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// Clear this thread from the exec mask if the operand is negative
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if ((Op.isImm() || Op.isFPImm())) {
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// Constant operand: Set exec mask to 0 or do nothing
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if (Op.isImm() ? (Op.getImm() & 0x80000000) :
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Op.getFPImm()->isNegative()) {
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
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.addImm(0);
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}
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} else {
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
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.addImm(0)
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.addOperand(Op);
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}
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MI.eraseFromParent();
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}
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/// The m0 register stores the maximum allowable address for LDS reads and
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/// writes. Its value must be at least the size in bytes of LDS allocated by
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/// the shader. For simplicity, we set it to the maximum possible value.
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void SILowerControlFlowPass::InitM0ForLDS(MachineBasicBlock::iterator MI) {
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BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
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AMDGPU::M0).addImm(0xffffffff);
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}
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void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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MachineBasicBlock::iterator I = MI;
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unsigned Save = MI.getOperand(1).getReg();
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unsigned Idx = MI.getOperand(3).getReg();
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if (AMDGPU::SReg_32RegClass.contains(Idx)) {
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
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.addReg(Idx);
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MBB.insert(I, MovRel);
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} else {
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assert(AMDGPU::SReg_64RegClass.contains(Save));
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assert(AMDGPU::VReg_32RegClass.contains(Idx));
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// Save the EXEC mask
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
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.addReg(AMDGPU::EXEC);
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// Read the next variant into VCC (lower 32 bits) <- also loop target
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
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AMDGPU::VCC_LO)
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.addReg(Idx);
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// Move index from VCC into M0
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
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.addReg(AMDGPU::VCC_LO);
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// Compare the just read M0 value to all possible Idx values
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
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.addReg(AMDGPU::M0)
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.addReg(Idx);
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// Update EXEC, save the original EXEC value to VCC
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
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.addReg(AMDGPU::VCC);
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// Do the actual move
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MBB.insert(I, MovRel);
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// Update EXEC, switch all done bits to 0 and all todo bits to 1
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(AMDGPU::VCC);
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// Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
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.addImm(-7)
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.addReg(AMDGPU::EXEC);
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// Restore EXEC
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
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.addReg(Save);
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}
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// FIXME: Are there any values other than the LDS address clamp that need to
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// be stored in the m0 register and may be live for more than a few
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// instructions? If so, we should save the m0 register at the beginning
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// of this function and restore it here.
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// FIXME: Add support for LDS direct loads.
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InitM0ForLDS(&MI);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Vec = MI.getOperand(2).getReg();
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unsigned Off = MI.getOperand(4).getImm();
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unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
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if (!SubReg)
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SubReg = Vec;
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MachineInstr *MovRel =
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BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
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.addReg(SubReg + Off)
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.addReg(AMDGPU::M0, RegState::Implicit)
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.addReg(Vec, RegState::Implicit);
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LoadM0(MI, MovRel);
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}
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void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Off = MI.getOperand(4).getImm();
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unsigned Val = MI.getOperand(5).getReg();
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unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
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if (!SubReg)
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SubReg = Dst;
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MachineInstr *MovRel =
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BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
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.addReg(SubReg + Off, RegState::Define)
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.addReg(Val)
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.addReg(AMDGPU::M0, RegState::Implicit)
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.addReg(Dst, RegState::Implicit);
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LoadM0(MI, MovRel);
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}
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bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
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TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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bool HaveKill = false;
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bool NeedM0 = false;
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bool NeedWQM = false;
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unsigned Depth = 0;
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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MachineBasicBlock::iterator I, Next;
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for (I = MBB.begin(); I != MBB.end(); I = Next) {
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Next = std::next(I);
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MachineInstr &MI = *I;
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if (TII->isDS(MI.getOpcode())) {
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NeedM0 = true;
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NeedWQM = true;
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}
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switch (MI.getOpcode()) {
|
|
default: break;
|
|
case AMDGPU::SI_IF:
|
|
++Depth;
|
|
If(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_ELSE:
|
|
Else(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_BREAK:
|
|
Break(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_IF_BREAK:
|
|
IfBreak(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_ELSE_BREAK:
|
|
ElseBreak(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_LOOP:
|
|
++Depth;
|
|
Loop(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_END_CF:
|
|
if (--Depth == 0 && HaveKill) {
|
|
SkipIfDead(MI);
|
|
HaveKill = false;
|
|
}
|
|
EndCf(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_KILL:
|
|
if (Depth == 0)
|
|
SkipIfDead(MI);
|
|
else
|
|
HaveKill = true;
|
|
Kill(MI);
|
|
break;
|
|
|
|
case AMDGPU::S_BRANCH:
|
|
Branch(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_INDIRECT_SRC:
|
|
IndirectSrc(MI);
|
|
break;
|
|
|
|
case AMDGPU::SI_INDIRECT_DST_V1:
|
|
case AMDGPU::SI_INDIRECT_DST_V2:
|
|
case AMDGPU::SI_INDIRECT_DST_V4:
|
|
case AMDGPU::SI_INDIRECT_DST_V8:
|
|
case AMDGPU::SI_INDIRECT_DST_V16:
|
|
IndirectDst(MI);
|
|
break;
|
|
|
|
case AMDGPU::V_INTERP_P1_F32:
|
|
case AMDGPU::V_INTERP_P2_F32:
|
|
case AMDGPU::V_INTERP_MOV_F32:
|
|
NeedWQM = true;
|
|
break;
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
if (NeedM0) {
|
|
MachineBasicBlock &MBB = MF.front();
|
|
// Initialize M0 to a value that won't cause LDS access to be discarded
|
|
// due to offset clamping
|
|
InitM0ForLDS(MBB.getFirstNonPHI());
|
|
}
|
|
|
|
if (NeedWQM && MFI->getShaderType() == ShaderType::PIXEL) {
|
|
MachineBasicBlock &MBB = MF.front();
|
|
BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
|
|
AMDGPU::EXEC).addReg(AMDGPU::EXEC);
|
|
}
|
|
|
|
return true;
|
|
}
|