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cac05d9b58
Summary: We can safely assume that the high bit of scratch offsets will never be set, because this would require at least 128 GB of GPU memory. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11225 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242433 91177308-0d34-0410-b5e6-96231b3b80d8
295 lines
10 KiB
TableGen
295 lines
10 KiB
TableGen
//===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Subtarget Features
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//===----------------------------------------------------------------------===//
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// Debugging Features
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def FeatureDumpCode : SubtargetFeature <"DumpCode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter">;
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def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter">;
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def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
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"EnableIRStructurizer",
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"false",
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"Disable IR Structurizer">;
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def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
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"EnablePromoteAlloca",
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"true",
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"Enable promote alloca pass">;
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// Target features
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def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
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"EnableIfCvt",
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"false",
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"Disable the if conversion pass">;
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def FeatureFP64 : SubtargetFeature<"fp64",
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"FP64",
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"true",
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"Enable double precision operations">;
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def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
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"FP64Denormals",
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"true",
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"Enable double precision denormal handling",
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[FeatureFP64]>;
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def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
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"FastFMAF32",
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"true",
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"Assuming f32 fma is at least as fast as mul + add",
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[]>;
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// Some instructions do not support denormals despite this flag. Using
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// fp32 denormals also causes instructions to run at the double
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// precision rate for the device.
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def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
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"FP32Denormals",
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"true",
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"Enable single precision denormal handling">;
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def Feature64BitPtr : SubtargetFeature<"64BitPtr",
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"Is64bit",
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"true",
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"Specify if 64-bit addressing should be used">;
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def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
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"R600ALUInst",
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"false",
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"Older version of ALU instructions encoding">;
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def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
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"HasVertexCache",
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"true",
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"Specify use of dedicated vertex cache">;
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def FeatureCaymanISA : SubtargetFeature<"caymanISA",
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"CaymanISA",
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"true",
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"Use Cayman ISA">;
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def FeatureCFALUBug : SubtargetFeature<"cfalubug",
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"CFALUBug",
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"true",
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"GPU has CF_ALU bug">;
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// XXX - This should probably be removed once enabled by default
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def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
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"EnableLoadStoreOpt",
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"true",
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"Enable SI load/store optimizer pass">;
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// Performance debugging feature. Allow using DS instruction immediate
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// offsets even if the base pointer can't be proven to be base. On SI,
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// base pointer values that won't give the same result as a 16-bit add
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// are not safe to fold, but this will override the conservative test
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// for the base pointer.
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def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <"unsafe-ds-offset-folding",
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"EnableUnsafeDSOffsetFolding",
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"true",
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"Force using DS instruction immediate offsets on SI">;
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def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
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"FlatAddressSpace",
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"true",
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"Support flat address space">;
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def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
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"EnableVGPRSpilling",
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"true",
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"Enable spilling of VGPRs to scratch memory">;
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def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
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"SGPRInitBug",
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"true",
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"VI SGPR initilization bug requiring a fixed SGPR allocation size">;
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def FeatureEnableHugeScratchBuffer : SubtargetFeature<"huge-scratch-buffer",
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"EnableHugeScratchBuffer",
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"true",
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"Enable scratch buffer sizes greater than 128 GB">;
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class SubtargetFeatureFetchLimit <string Value> :
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SubtargetFeature <"fetch"#Value,
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"TexVTXClauseSize",
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Value,
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"Limit the maximum number of fetches in a clause to "#Value>;
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def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
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def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
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class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
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"wavefrontsize"#Value,
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"WavefrontSize",
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!cast<string>(Value),
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"The number of threads per wavefront">;
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def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
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def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
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def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
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class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
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"ldsbankcount"#Value,
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"LDSBankCount",
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!cast<string>(Value),
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"The number of LDS banks per compute unit.">;
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def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
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def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
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class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
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: SubtargetFeature <
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"isaver"#Major#"."#Minor#"."#Stepping,
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"IsaVersion",
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"ISAVersion"#Major#"_"#Minor#"_"#Stepping,
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"Instruction set version number"
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>;
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def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
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def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
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def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
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def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
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class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
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"localmemorysize"#Value,
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"LocalMemorySize",
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!cast<string>(Value),
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"The size of local memory in bytes">;
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def FeatureGCN : SubtargetFeature<"gcn",
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"IsGCN",
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"true",
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"GCN or newer GPU">;
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def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
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"GCN1Encoding",
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"true",
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"Encoding format for SI and CI">;
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def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
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"GCN3Encoding",
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"true",
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"Encoding format for VI">;
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def FeatureCIInsts : SubtargetFeature<"ci-insts",
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"CIInsts",
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"true",
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"Additional intstructions for CI+">;
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// Dummy feature used to disable assembler instructions.
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def FeatureDisable : SubtargetFeature<"",
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"FeatureDisable","true",
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"Dummy feature to disable assembler"
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" instructions">;
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class SubtargetFeatureGeneration <string Value,
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list<SubtargetFeature> Implies> :
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SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
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Value#" GPU generation", Implies>;
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def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
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def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
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def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
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def FeatureR600 : SubtargetFeatureGeneration<"R600",
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[FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
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def FeatureR700 : SubtargetFeatureGeneration<"R700",
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[FeatureFetchLimit16, FeatureLocalMemorySize0]>;
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def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
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[FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
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def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
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[FeatureFetchLimit16, FeatureWavefrontSize64,
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FeatureLocalMemorySize32768]
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>;
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def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
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FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
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FeatureLDSBankCount32]>;
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
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FeatureGCN1Encoding, FeatureCIInsts]>;
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def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
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FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
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//===----------------------------------------------------------------------===//
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def AMDGPUInstrInfo : InstrInfo {
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let guessInstructionProperties = 1;
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let noNamedPositionallyEncodedOperands = 1;
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}
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def AMDGPUAsmParser : AsmParser {
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// Some of the R600 registers have the same name, so this crashes.
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// For example T0_XYZW and T0_XY both have the asm name T0.
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let ShouldEmitMatchRegisterName = 0;
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}
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def AMDGPU : Target {
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// Pull in Instruction Info:
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let InstructionSet = AMDGPUInstrInfo;
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let AssemblyParsers = [AMDGPUAsmParser];
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}
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// Dummy Instruction itineraries for pseudo instructions
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def ALU_NULL : FuncUnit;
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def NullALU : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Predicate helper class
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//===----------------------------------------------------------------------===//
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def TruePredicate : Predicate<"true">;
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def isSICI : Predicate<
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"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
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"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
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>, AssemblerPredicate<"FeatureGCN1Encoding">;
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class PredicateControl {
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Predicate SubtargetPredicate;
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Predicate SIAssemblerPredicate = isSICI;
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list<Predicate> AssemblerPredicates = [];
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Predicate AssemblerPredicate = TruePredicate;
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list<Predicate> OtherPredicates = [];
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list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
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AssemblerPredicates,
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OtherPredicates);
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}
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// Include AMDGPU TD files
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include "R600Schedule.td"
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include "SISchedule.td"
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include "Processors.td"
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include "AMDGPUInstrInfo.td"
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include "AMDGPUIntrinsics.td"
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include "AMDGPURegisterInfo.td"
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include "AMDGPUInstructions.td"
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include "AMDGPUCallingConv.td"
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