Oliver Stannard 8a4fa4a92d [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled ...

When branch target identification is enabled, we can only do indirect
tail-calls through x16 or x17. This means that the outliner can't
transform a BLR instruction at the end of an outlined region into a BR.

Differential revision: https://reviews.llvm.org/D52869



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343969 91177308-0d34-0410-b5e6-96231b3b80d8

2018-10-08 14:12:08 +00:00

..

AArch64

[AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled

2018-10-08 14:12:08 +00:00

AMDGPU

AMDGPU/GlobalISel: Add support for G_INTTOPTR

2018-10-05 04:34:09 +00:00

ARC

…

ARM

[ARM] Account for implicit IT when calculating inline asm size

2018-10-08 09:38:28 +00:00

AVR

[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'

2018-09-01 12:23:00 +00:00

BPF

[bpf] Test case for symbol information in object file

2018-09-22 17:31:01 +00:00

Generic

Re-submitting changes in D51550 because it failed to patch.

2018-09-24 20:47:12 +00:00

Hexagon

[Hexagon] Fix extracting subvectors of non-HVX vNi1

2018-10-02 15:05:43 +00:00

Inputs

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Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[mips] Remove -allow-deprecated-dag-overlap flag from tests. NFC

2018-10-03 22:02:23 +00:00

MIR

[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL

2018-10-01 21:59:45 +00:00

MSP430

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

[PowerPC] Folding XForm to DForm loads requires alignment for some DForm loads.

2018-10-01 20:16:27 +00:00

RISCV

[RISCV] Update alu8.ll and alu16.ll test cases

2018-10-08 09:08:51 +00:00

SPARC

[Sparc] Remove the support for builtin setjmp/longjmp

2018-09-27 13:32:54 +00:00

SystemZ

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Thumb

Revert "Revert "[ConstHoist] Do not rebase single (or few) dependent constant""

2018-09-26 00:59:09 +00:00

Thumb2

[ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33

2018-09-24 12:02:50 +00:00

WebAssembly

[WebAssembly] Saturating arithmetic intrinsics

2018-10-05 00:45:20 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[GlobalIsel][X86] Support G_UDIV/G_UREM/G_SREM

2018-10-08 13:40:34 +00:00

XCore

[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

2018-07-15 16:27:07 +00:00