Daniel Sanders 77ae274ae7 [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 ...

Summary:
There is no change to the restrictions, just the result register is stored
once in the encoding rather than twice. The rt field is zero in
MIPS32r6/MIPS64r6.

Depends on D4119

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4120

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211019 91177308-0d34-0410-b5e6-96231b3b80d8

2014-06-16 13:18:59 +00:00

..

msa

[mips] Move disassembler test (test_2r_msa64) into correct folder.

2014-05-12 16:59:34 +00:00

lit.local.cfg

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

micromips_le.txt

LL and SC decoder method fix.

2014-01-15 13:17:33 +00:00

micromips.txt

LL and SC decoder method fix.

2014-01-15 13:17:33 +00:00

mips32_le.txt

This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.

2014-03-03 13:12:59 +00:00

mips32.txt

This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.

2014-03-03 13:12:59 +00:00

mips32r2_le.txt

This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.

2014-03-03 13:12:59 +00:00

mips32r2.txt

This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.

2014-03-03 13:12:59 +00:00

mips32r6.txt

[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6

2014-06-16 13:18:59 +00:00

mips64_le.txt

[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.

2013-08-28 00:55:15 +00:00

mips64.txt

Mips: Disassemble sign-extended 64 bit immediates properly.

2013-10-11 19:05:08 +00:00

mips64r2_le.txt

Use object file specific section type for initial text section

2013-04-14 21:18:36 +00:00

mips64r2.txt

Use object file specific section type for initial text section

2013-04-14 21:18:36 +00:00

mips64r6.txt

[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6

2014-06-16 13:18:59 +00:00

mips-dsp.txt

[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.

2013-08-28 00:55:15 +00:00