mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-19 15:13:49 -04:00
Nikita Popov
37e240c2fe
This is part of https://bugs.llvm.org/show_bug.cgi?id=40442. Vector legalization is implemented for the add/sub overflow opcodes. UMULO/SMULO are also handled as far as legalization is concerned, but they don't support vector expansion yet (so no tests for them). The vector result widening implementation is suboptimal, because it could result in a legalization loop. Differential Revision: https://reviews.llvm.org/D57639 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353464 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
4.2 KiB
LLVM
93 lines
4.2 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
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declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
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declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
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declare { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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; FUNC-LABEL: {{^}}ssubo_i64_zext:
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define amdgpu_kernel void @ssubo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %ssub, 0
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%carry = extractvalue { i64, i1 } %ssub, 1
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%ext = zext i1 %carry to i64
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%add2 = add i64 %val, %ext
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store i64 %add2, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_ssubo_i32:
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define amdgpu_kernel void @s_ssubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) nounwind {
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%ssub = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind
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%val = extractvalue { i32, i1 } %ssub, 0
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%carry = extractvalue { i32, i1 } %ssub, 1
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_ssubo_i32:
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define amdgpu_kernel void @v_ssubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%a = load i32, i32 addrspace(1)* %aptr, align 4
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%b = load i32, i32 addrspace(1)* %bptr, align 4
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%ssub = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind
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%val = extractvalue { i32, i1 } %ssub, 0
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%carry = extractvalue { i32, i1 } %ssub, 1
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}s_ssubo_i64:
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; GCN: s_sub_u32
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; GCN: s_subb_u32
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define amdgpu_kernel void @s_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind {
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%ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %ssub, 0
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%carry = extractvalue { i64, i1 } %ssub, 1
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store i64 %val, i64 addrspace(1)* %out, align 8
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_ssubo_i64:
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; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
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; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc,
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define amdgpu_kernel void @v_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
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%a = load i64, i64 addrspace(1)* %aptr, align 4
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%b = load i64, i64 addrspace(1)* %bptr, align 4
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%ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %ssub, 0
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%carry = extractvalue { i64, i1 } %ssub, 1
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store i64 %val, i64 addrspace(1)* %out, align 8
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_ssubo_v2i32:
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_sub_{{[iu]}}32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_sub_{{[iu]}}32
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define amdgpu_kernel void @v_ssubo_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %carryout, <2 x i32> addrspace(1)* %aptr, <2 x i32> addrspace(1)* %bptr) nounwind {
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%a = load <2 x i32>, <2 x i32> addrspace(1)* %aptr, align 4
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%b = load <2 x i32>, <2 x i32> addrspace(1)* %bptr, align 4
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%sadd = call { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b) nounwind
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%val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0
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%carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1
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store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4
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%carry.ext = zext <2 x i1> %carry to <2 x i32>
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store <2 x i32> %carry.ext, <2 x i32> addrspace(1)* %carryout
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ret void
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}
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