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https://github.com/RPCS3/llvm.git
synced 2026-07-19 15:13:49 -04:00
Florian Hahn
6c41152656
Currently this test causes test failures on some machines, due to isel not being registered. Update the test to run all passes and check emitted assembly instructions for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311545 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
1.2 KiB
LLVM
35 lines
1.2 KiB
LLVM
; RUN: llc -mtriple armv8-unknown-linux -o - < %s | FileCheck %s
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define <2 x float> @test_float(<6 x float>* %src) {
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%v= load <6 x float>, <6 x float>* %src, align 1
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%r = shufflevector <6 x float> %v, <6 x float> undef, <2 x i32> <i32 2, i32 5>
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ret <2 x float> %r
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}
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; CHECK-LABEL: test_float
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; CHECK: vld3.32 {d16, d17, d18}, [r0]
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define <2 x i32> @test_i32(<6 x i32>* %src) {
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%v= load <6 x i32>, <6 x i32>* %src, align 1
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%r = shufflevector <6 x i32> %v, <6 x i32> undef, <2 x i32> <i32 2, i32 5>
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ret <2 x i32> %r
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}
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; CHECK-LABEL: test_i32
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; CHECK: vld3.32 {d16, d17, d18}, [r0]
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define <4 x i16> @test_i16(<12 x i16>* %src) {
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%v= load <12 x i16>, <12 x i16>* %src, align 1
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%r = shufflevector <12 x i16> %v, <12 x i16> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 7>
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ret <4 x i16> %r
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}
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; CHECK-LABEL: test_i16
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; CHECK: vld1.8 {d16, d17}, [r0]!
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; CHECK: vmov.u16 r1, d16[2]
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define <8 x i8> @test_i8(<24 x i8>* %src) {
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%v= load <24 x i8>, <24 x i8>* %src, align 1
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%r = shufflevector <24 x i8> %v, <24 x i8> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
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ret <8 x i8> %r
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}
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; CHECK-LABEL: test_i8
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; CHECK: vld3.8 {d16, d17, d18}, [r0]
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