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https://github.com/RPCS3/llvm.git
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David Green
7135d8b482
Adds fatal errors for any target that does not support the Tiny or Kernel codemodels by rejigging the getEffectiveCodeModel calls. Differential Revision: https://reviews.llvm.org/D50141 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348585 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.7 KiB
LLVM
50 lines
1.7 KiB
LLVM
; RUN: llc -march=lanai < %s | FileCheck %s
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; RUN: llc -march=lanai < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s
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; RUN: not llc -march=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s
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; RUN: not llc -march=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s
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; CHECK-TINY: Target does not support the tiny CodeModel
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; CHECK-KERNEL: Target does not support the kernel CodeModel
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@data = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
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define i32 @foo() nounwind readonly {
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entry:
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; CHECK-SMALL-LABEL: foo:
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; CHECK-SMALL: ld [data], %rv
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; CHECK-LABEL: foo:
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; CHECK: mov hi(data), %r[[REGISTER:[0-9]+]]
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; CHECK: or %r[[REGISTER]], lo(data), %r[[REGISTER]]
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; CHECK: ld 0[%r[[REGISTER]]], %rv
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%0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0), align 4 ; <i32> [#uses=1]
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ret i32 %0
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}
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define i32 @foo1() nounwind readonly {
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entry:
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; CHECK-SMALL-LABEL: foo1:
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; CHECK-SMALL: mov data, %r[[REGISTER:[0-9]+]]
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; CHECK-SMALL: ld 40[%r[[REGISTER]]], %rv
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; CHECK-LABEL: foo1:
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; CHECK: mov hi(data), %r[[REGISTER:[0-9]+]]
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; CHECK: or %r[[REGISTER]], lo(data), %r[[REGISTER]]
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; CHECK: ld 40[%r[[REGISTER]]], %rv
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%0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i32 0, i64 10), align 4 ; <i32> [#uses=1]
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ret i32 %0
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}
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@y = local_unnamed_addr global i32* null, section ".ldata,block", align 8
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define i32 @foo2() nounwind readonly {
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entry:
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; CHECK-SMALL-LABEL: foo2:
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; CHECK-SMALL: mov hi(y), %r[[REGISTER:[0-9]+]]
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; CHECK-SMALL: or %r[[REGISTER]], lo(y), %r[[REGISTER]]
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; CHECK-LABEL: foo2:
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; CHECK: mov hi(y), %r[[REGISTER:[0-9]+]]
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; CHECK: or %r[[REGISTER]], lo(y), %r[[REGISTER]]
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%0 = load i32*, i32** @y, align 8
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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