mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-19 23:23:38 -04:00
Zi Xuan Wu
fc1bf1b19a
A shift and add/sub sequence combination is faster in place of a multiply by constant. Because the cycle or latency of multiply is not huge, we only consider such following worthy patterns. ``` (mul x, 2^N + 1) => (add (shl x, N), x) (mul x, -(2^N + 1)) => -(add (shl x, N), x) (mul x, 2^N - 1) => (sub (shl x, N), x) (mul x, -(2^N - 1)) => (sub x, (shl x, N)) ``` And the cycles or latency is subtarget-dependent so that we need consider the subtarget to determine to do or not do such transformation. Also data type is considered for different cycles or latency to do multiply. Differential Revision: https://reviews.llvm.org/D58950 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357233 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
2.3 KiB
LLVM
80 lines
2.3 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=ppc64-- | FileCheck %s -check-prefixes=PWR8-CHECK,CHECK
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=ppc64le-- | FileCheck %s -check-prefixes=PWR9-CHECK,CHECK
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define i32 @test1(i32 %a) {
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%tmp.1 = mul nsw i32 %a, 16 ; <i32> [#uses=1]
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ret i32 %tmp.1
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}
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; CHECK-LABEL: test1:
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; CHECK-NOT: mul
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; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
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define i32 @test2(i32 %a) {
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%tmp.1 = mul nsw i32 %a, 17 ; <i32> [#uses=1]
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ret i32 %tmp.1
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}
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; CHECK-LABEL: test2:
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; CHECK-NOT: mul
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; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
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; CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]]
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define i32 @test3(i32 %a) {
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%tmp.1 = mul nsw i32 %a, 15 ; <i32> [#uses=1]
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ret i32 %tmp.1
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}
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; CHECK-LABEL: test3:
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; CHECK-NOT: mul
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; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
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; CHECK-NEXT: subf r[[REG2:[0-9]+]], r3, r[[REG1]]
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; negtive constant
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define i32 @test4(i32 %a) {
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%tmp.1 = mul nsw i32 %a, -16 ; <i32> [#uses=1]
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ret i32 %tmp.1
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}
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; CHECK-LABEL: test4:
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; CHECK-NOT: mul
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; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
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; CHECK-NEXT: neg r[[REG2:[0-9]+]], r[[REG1]]
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define i32 @test5(i32 %a) {
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%tmp.1 = mul nsw i32 %a, -17 ; <i32> [#uses=1]
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ret i32 %tmp.1
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}
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; CHECK-LABEL: test5:
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; PWR9-CHECK: mulli r[[REG1:[0-9]+]], r3, -17
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; PWR8-CHECK-NOT: mul
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; PWR8-CHECK: slwi r[[REG1:[0-9]+]], r3, 4
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; PWR8-CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]]
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; PWR8-CHECK-NEXT: neg r{{[0-9]+}}, r[[REG2]]
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define i32 @test6(i32 %a) {
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%tmp.1 = mul nsw i32 %a, -15 ; <i32> [#uses=1]
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ret i32 %tmp.1
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}
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; CHECK-LABEL: test6:
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; CHECK-NOT: mul
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; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
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; CHECK-NEXT: subf r[[REG2:[0-9]+]], r[[REG1]], r3
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; CHECK-NOT: neg
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; boundary case
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define i32 @test7(i32 %a) {
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%tmp.1 = mul nsw i32 %a, -2147483648 ; <i32> [#uses=1]
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ret i32 %tmp.1
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}
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; CHECK-LABEL: test7:
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; CHECK-NOT: mul
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; CHECK: slwi r[[REG1:[0-9]+]], r3, 31
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define i32 @test8(i32 %a) {
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%tmp.1 = mul nsw i32 %a, 2147483647 ; <i32> [#uses=1]
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ret i32 %tmp.1
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}
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; CHECK-LABEL: test8:
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; CHECK-NOT: mul
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; CHECK: slwi r[[REG1:[0-9]+]], r3, 31
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; CHECK-NEXT: subf r[[REG2:[0-9]+]], r3, r[[REG1]]
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