mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-19 23:23:38 -04:00
David Green
c399770b5c
Similar to D67327, but this time for the FP16 VLDR and VSTR instructions that use the AddrMode5FP16 addressing mode. We need to reserve an emergency spill slot for instructions that will be out of range to use sp directly. AddrMode5FP16 is 8 bits with a scale of 2. Differential Revision: https://reviews.llvm.org/D67483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372132 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
3.4 KiB
YAML
96 lines
3.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fullfp16 -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
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---
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name: func0
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tracksRegLiveness: true
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stack:
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- { id: 0, name: '', type: default, offset: 0, size: 2, alignment: 2,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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- { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -2, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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body: |
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bb.0:
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; CHECK-LABEL: name: func0
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; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
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; CHECK: $sp = frame-setup t2SUBri killed $sp, 1208, 14, $noreg, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1244
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; CHECK: $r0 = IMPLICIT_DEF
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; CHECK: $r1 = IMPLICIT_DEF
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; CHECK: $r2 = IMPLICIT_DEF
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; CHECK: $r3 = IMPLICIT_DEF
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; CHECK: $r4 = IMPLICIT_DEF
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; CHECK: $r5 = IMPLICIT_DEF
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; CHECK: $r6 = IMPLICIT_DEF
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; CHECK: $r7 = IMPLICIT_DEF
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; CHECK: $r8 = IMPLICIT_DEF
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; CHECK: $r9 = IMPLICIT_DEF
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; CHECK: $r10 = IMPLICIT_DEF
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; CHECK: $r11 = IMPLICIT_DEF
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; CHECK: $r12 = IMPLICIT_DEF
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; CHECK: $lr = IMPLICIT_DEF
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; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2)
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; CHECK: $r0 = t2ADDri killed $sp, 1024, 14, $noreg, $noreg
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; CHECK: renamable $s4 = VLDRH killed $r0, 91, 14, $noreg :: (dereferenceable load 2 from %stack.0)
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; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2)
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; CHECK: KILL $r0
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; CHECK: KILL $r1
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; CHECK: KILL $r2
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; CHECK: KILL $r3
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; CHECK: KILL $r4
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; CHECK: KILL $r5
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; CHECK: KILL $r6
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; CHECK: KILL $r7
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; CHECK: KILL $r8
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; CHECK: KILL $r9
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; CHECK: KILL $r10
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; CHECK: KILL $r11
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; CHECK: KILL $r12
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; CHECK: KILL $lr
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$r0 = IMPLICIT_DEF
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$r1 = IMPLICIT_DEF
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$r2 = IMPLICIT_DEF
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$r3 = IMPLICIT_DEF
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$r4 = IMPLICIT_DEF
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$r5 = IMPLICIT_DEF
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$r6 = IMPLICIT_DEF
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$r7 = IMPLICIT_DEF
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$r8 = IMPLICIT_DEF
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$r9 = IMPLICIT_DEF
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$r10 = IMPLICIT_DEF
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$r11 = IMPLICIT_DEF
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$r12 = IMPLICIT_DEF
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$lr = IMPLICIT_DEF
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renamable $s4 = VLDRH %stack.0, 0, 14, $noreg :: (dereferenceable load 2 from %stack.0)
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KILL $r0
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KILL $r1
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KILL $r2
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KILL $r3
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KILL $r4
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KILL $r5
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KILL $r6
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KILL $r7
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KILL $r8
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KILL $r9
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KILL $r10
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KILL $r11
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KILL $r12
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KILL $lr
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...
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