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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
961 B
LLVM
38 lines
961 B
LLVM
; RUN: llc < %s -march=arm64
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; Make sure we are not crashing on this test.
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define void @autogen_SD12881() {
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BB:
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%B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
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br label %CF
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CF: ; preds = %CF83, %CF, %BB
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br i1 undef, label %CF, label %CF83
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CF83: ; preds = %CF
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%FC70 = sitofp <4 x i32> %B17 to <4 x double>
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br label %CF
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}
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define void @autogen_SD12881_2() {
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BB:
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%B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
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br label %CF
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CF: ; preds = %CF83, %CF, %BB
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br i1 undef, label %CF, label %CF83
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CF83: ; preds = %CF
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%FC70 = uitofp <4 x i32> %B17 to <4 x double>
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br label %CF
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}
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define void @_Z12my_example2bv() nounwind noinline ssp {
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entry:
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%0 = fptosi <2 x double> undef to <2 x i32>
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store <2 x i32> %0, <2 x i32>* undef, align 8
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ret void
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}
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