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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
2.6 KiB
LLVM
87 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false < %s | FileCheck %s
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@var = global i32 0, align 4
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define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
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store i32 %after, i32* @var, align 4
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; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
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ret i128 %arg
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; CHECK: mov x0, x2
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; CHECK: mov x1, x3
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}
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@var64 = global i64 0, align 8
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; Check stack slots are 64-bit at all times.
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define void @test_stack_slots([8 x i32], i1 %bool, i8 %char, i16 %short,
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i32 %int, i64 %long) {
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; Part of last store. Blasted scheduler.
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; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32]
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%ext_bool = zext i1 %bool to i64
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store volatile i64 %ext_bool, i64* @var64, align 8
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; CHECK: ldr w[[EXT:[0-9]+]], [sp]
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; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1
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; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
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%ext_char = zext i8 %char to i64
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store volatile i64 %ext_char, i64* @var64, align 8
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; CHECK: ldrb w[[EXT:[0-9]+]], [sp, #8]
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; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_short = zext i16 %short to i64
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store volatile i64 %ext_short, i64* @var64, align 8
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; CHECK: ldrh w[[EXT:[0-9]+]], [sp, #16]
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; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_int = zext i32 %int to i64
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store volatile i64 %ext_int, i64* @var64, align 8
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; CHECK: ldr w[[EXT:[0-9]+]], [sp, #24]
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; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
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store volatile i64 %long, i64* @var64, align 8
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; CHECK: str [[LONG]], [{{x[0-9]+}}, :lo12:var64]
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ret void
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}
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; Make sure the callee does extensions (in the absence of zext/sext
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; keyword on args) while we're here.
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define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
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%ext_bool = zext i1 %bool to i64
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store volatile i64 %ext_bool, i64* @var64
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; CHECK: and [[EXT:x[0-9]+]], x0, #0x1
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_char = sext i8 %char to i64
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store volatile i64 %ext_char, i64* @var64
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; CHECK: sxtb [[EXT:x[0-9]+]], x1
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_short = zext i16 %short to i64
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store volatile i64 %ext_short, i64* @var64
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; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_int = zext i32 %int to i64
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store volatile i64 %ext_int, i64* @var64
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; CHECK: uxtw [[EXT:x[0-9]+]], x3
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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ret void
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}
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declare void @variadic(i32 %a, ...)
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; Under AAPCS variadic functions have the same calling convention as
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; others. The extra arguments should go in registers rather than on the stack.
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define void @test_variadic() {
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call void(i32, ...)* @variadic(i32 0, i64 1, double 2.0)
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; CHECK: fmov d0, #2.0
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; CHECK: orr x1, xzr, #0x1
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; CHECK: bl variadic
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ret void
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}
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