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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
682 B
LLVM
23 lines
682 B
LLVM
; RUN: llc -march=arm64 -o - %s | FileCheck %s
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; ARM64ISelLowering.cpp was creating a new (floating-point) load for efficiency
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; but not updating chain-successors of the old one. As a result, the two memory
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; operations in this function both ended up direct successors to the EntryToken
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; and could be reordered.
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@var = global i32 0, align 4
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define float @foo() {
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; CHECK-LABEL: foo:
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; Load must come before we clobber @var
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; CHECK: adrp x[[VARBASE:[0-9]+]], {{_?var}}
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; CHECK: ldr [[SREG:s[0-9]+]], [x[[VARBASE]],
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; CHECK: str wzr, [x[[VARBASE]],
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%val = load i32* @var, align 4
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store i32 0, i32* @var, align 4
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%fltval = sitofp i32 %val to float
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ret float %fltval
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}
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