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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.0 KiB
LLVM
42 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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; rdar://r11231896
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define void @t1(i8* nocapture %a, i8* nocapture %b) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK-NOT: orr
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; CHECK: ldr [[X0:x[0-9]+]], [x1]
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; CHECK: str [[X0]], [x0]
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%tmp1 = bitcast i8* %b to i64*
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%tmp2 = bitcast i8* %a to i64*
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%tmp3 = load i64* %tmp1, align 1
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store i64 %tmp3, i64* %tmp2, align 1
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ret void
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}
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define void @t2(i8* nocapture %a, i8* nocapture %b) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK-NOT: orr
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; CHECK: ldr [[W0:w[0-9]+]], [x1]
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; CHECK: str [[W0]], [x0]
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%tmp1 = bitcast i8* %b to i32*
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%tmp2 = bitcast i8* %a to i32*
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%tmp3 = load i32* %tmp1, align 1
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store i32 %tmp3, i32* %tmp2, align 1
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ret void
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}
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define void @t3(i8* nocapture %a, i8* nocapture %b) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK-NOT: orr
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; CHECK: ldrh [[W0:w[0-9]+]], [x1]
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; CHECK: strh [[W0]], [x0]
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%tmp1 = bitcast i8* %b to i16*
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%tmp2 = bitcast i8* %a to i16*
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%tmp3 = load i16* %tmp1, align 1
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store i16 %tmp3, i16* %tmp2, align 1
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ret void
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}
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