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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
2.7 KiB
LLVM
83 lines
2.7 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_f64_f32:
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%vcvt1.i = fpext <2 x float> %x to <2 x double>
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; CHECK: fcvtl v0.2d, v0.2s
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ret <2 x double> %vcvt1.i
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; CHECK: ret
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}
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define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_f64_f32:
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%cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3>
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%vcvt1.i = fpext <2 x float> %cvt_in to <2 x double>
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; CHECK: fcvtl2 v0.2d, v0.4s
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ret <2 x double> %vcvt1.i
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; CHECK: ret
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}
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define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_f32_f64:
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%vcvt1.i = fptrunc <2 x double> %v to <2 x float>
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; CHECK: fcvtn
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ret <2 x float> %vcvt1.i
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; CHECK: ret
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}
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define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_f32_f64:
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%cvt = fptrunc <2 x double> %v to <2 x float>
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%vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK: fcvtn2
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ret <4 x float> %vcvt2.i
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; CHECK: ret
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}
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define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvtx_f32_f64:
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%vcvtx1.i = tail call <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
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; CHECK: fcvtxn
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ret <2 x float> %vcvtx1.i
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; CHECK: ret
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}
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define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvtx_high_f32_f64:
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%vcvtx2.i = tail call <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
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%res = shufflevector <2 x float> %x, <2 x float> %vcvtx2.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK: fcvtxn2
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ret <4 x float> %res
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; CHECK: ret
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}
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declare <2 x double> @llvm.arm64.neon.vcvthighfp2df(<4 x float>) nounwind readnone
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declare <2 x double> @llvm.arm64.neon.vcvtfp2df(<2 x float>) nounwind readnone
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declare <2 x float> @llvm.arm64.neon.vcvtdf2fp(<2 x double>) nounwind readnone
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declare <4 x float> @llvm.arm64.neon.vcvthighdf2fp(<2 x float>, <2 x double>) nounwind readnone
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declare <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
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define i16 @to_half(float %in) {
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; CHECK-LABEL: to_half:
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; CHECK: fcvt h[[HALFVAL:[0-9]+]], s0
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; CHECK: fmov w0, s[[HALFVAL]]
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%res = call i16 @llvm.convert.to.fp16(float %in)
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ret i16 %res
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}
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define float @from_half(i16 %in) {
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; CHECK-LABEL: from_half:
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; CHECK: fmov s[[HALFVAL:[0-9]+]], {{w[0-9]+}}
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; CHECK: fcvt s0, h[[HALFVAL]]
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%res = call float @llvm.convert.from.fp16(i16 %in)
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ret float %res
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}
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declare float @llvm.convert.from.fp16(i16) #1
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declare i16 @llvm.convert.to.fp16(float) #1
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