Jim Grosbach 7bf504c58f ARM: Creating a vector from a lane of another. ...

The VDUP instruction source register doesn't allow a non-constant lane
index, so make sure we don't construct a ARM::VDUPLANE node asking it to
do so.

rdar://13328063
http://llvm.org/bugs/show_bug.cgi?id=13963

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8

2013-03-02 20:16:24 +00:00

..

AArch64

AArch64: be more careful resorting to inefficient addressing for weak vars.

2013-02-28 14:36:31 +00:00

ARM

ARM NEON: Fix v2f32 float intrinsics

2013-03-02 19:38:33 +00:00

CPP

…

Generic

For inline asm:

2013-01-11 18:12:39 +00:00

Hexagon

Hexagon: Add constant extender support framework.

2013-03-01 17:37:13 +00:00

MBlaze

…

Mips

[mips] Fix inefficient code generation.

2013-03-01 21:52:08 +00:00

MSP430

Add support for varargs functions for msp430.

2012-11-21 17:28:27 +00:00

NVPTX

[NVPTX] Disable vector registers

2013-02-12 14:18:49 +00:00

PowerPC

Fix PR15332 (patch by Florian Zeitz).

2013-02-26 21:28:57 +00:00

R600

R600/SI: fix sampler tests after fixing wait insertions

2013-03-01 17:39:05 +00:00

SI

Add R600 backend

2012-12-11 21:25:42 +00:00

SPARC

…

Thumb

Revert "Rewrite a test to count emitted instructions without using -stats"

2013-03-02 00:53:20 +00:00

Thumb2

ARM: Creating a vector from a lane of another.

2013-03-02 20:16:24 +00:00

X86

Add regression tests (WORKSFORME)

2013-03-01 19:23:37 +00:00

XCore

Fix handling of aliases to functions.

2012-11-16 21:12:38 +00:00