Jonas Hahnfeld ba19c689aa [NVPTX] Assign valid global names ...

PTX requires that identifiers consist only of [a-zA-Z0-9_$]. The
existing pass already ensured this for globals and this patch adds
the cleanup for functions with local linkage.

However, there was a different problem in the case of collisions
of the adjusted name: The ValueSymbolTable then automatically
appended ".N" with increasing Ns to get a unique name while helping
the ABI demangling. Special case this behavior to omit the dots and
append N directly. This will always give us legal names according
to the PTX requirements.

Differential Revision: https://reviews.llvm.org/D40573

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319657 91177308-0d34-0410-b5e6-96231b3b80d8

2017-12-04 14:19:33 +00:00

..

AArch64

[AArch64] Allow using emulated tls on platforms other than ELF

2017-12-04 09:09:04 +00:00

AMDGPU

CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr space

2017-12-03 03:31:45 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Allow using emulated tls on platforms other than ELF

2017-12-04 09:08:55 +00:00

AVR

[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

2017-11-30 12:12:19 +00:00

BPF

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

Generic

Support generic lowering of vector bswap

2017-11-30 11:06:22 +00:00

Hexagon

[Hexagon] Fix wrong check in test/CodeGen/Hexagon/newvaluejump-solo.mir

2017-11-30 21:23:19 +00:00

Inputs

…

Lanai

[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

2017-11-30 12:12:19 +00:00

Mips

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

MIR

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

MSP430

[DAG] Improve Aliasing of operations to static alloca

2017-07-18 20:06:24 +00:00

Nios2

[Nios2] Target registration

2017-05-29 09:48:30 +00:00

NVPTX

[NVPTX] Assign valid global names

2017-12-04 14:19:33 +00:00

PowerPC

Follow-up to r319434 to turn the pass on by default

2017-12-01 12:02:59 +00:00

RISCV

[RISCV] Use register X0 (ZERO) for constant 0

2017-11-21 08:23:08 +00:00

SPARC

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

SystemZ

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

Thumb

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

Thumb2

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

WebAssembly

[WebAssembly] Revert r319186 "Support bitcasted function addresses with varargs."

2017-11-30 18:16:49 +00:00

WinEH

Make x86 __ehhandler comdat if parent function is

2017-10-20 17:04:43 +00:00

X86

[X86] Allow VPMAXUQ/VPMAXSQ/VPMINUQ/VPMINSQ to be used with 128/256 bit vectors when AVX512 is enabled.

2017-12-04 07:21:01 +00:00

XCore

[MC] Suppress .Lcfi labels when emitting textual assembly

2017-10-10 00:57:36 +00:00