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803 lines
24 KiB
C++
803 lines
24 KiB
C++
//===-------------- MIRCanonicalizer.cpp - MIR Canonicalizer --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The purpose of this pass is to employ a canonical code transformation so
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// that code compiled with slightly different IR passes can be diffed more
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// effectively than otherwise. This is done by renaming vregs in a given
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// LiveRange in a canonical way. This pass also does a pseudo-scheduling to
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// move defs closer to their use inorder to reduce diffs caused by slightly
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// different schedules.
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//
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// Basic Usage:
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//
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// llc -o - -run-pass mir-canonicalizer example.mir
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//
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// Reorders instructions canonically.
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// Renames virtual register operands canonically.
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// Strips certain MIR artifacts (optionally).
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/raw_ostream.h"
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#include <queue>
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using namespace llvm;
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namespace llvm {
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extern char &MIRCanonicalizerID;
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} // namespace llvm
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#define DEBUG_TYPE "mir-canonicalizer"
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static cl::opt<unsigned>
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CanonicalizeFunctionNumber("canon-nth-function", cl::Hidden, cl::init(~0u),
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cl::value_desc("N"),
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cl::desc("Function number to canonicalize."));
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static cl::opt<unsigned> CanonicalizeBasicBlockNumber(
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"canon-nth-basicblock", cl::Hidden, cl::init(~0u), cl::value_desc("N"),
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cl::desc("BasicBlock number to canonicalize."));
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namespace {
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class MIRCanonicalizer : public MachineFunctionPass {
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public:
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static char ID;
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MIRCanonicalizer() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override {
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return "Rename register operands in a canonical ordering.";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // end anonymous namespace
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enum VRType { RSE_Reg = 0, RSE_FrameIndex, RSE_NewCandidate };
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class TypedVReg {
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VRType type;
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unsigned reg;
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public:
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TypedVReg(unsigned reg) : type(RSE_Reg), reg(reg) {}
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TypedVReg(VRType type) : type(type), reg(~0U) {
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assert(type != RSE_Reg && "Expected a non-register type.");
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}
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bool isReg() const { return type == RSE_Reg; }
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bool isFrameIndex() const { return type == RSE_FrameIndex; }
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bool isCandidate() const { return type == RSE_NewCandidate; }
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VRType getType() const { return type; }
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unsigned getReg() const {
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assert(this->isReg() && "Expected a virtual or physical register.");
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return reg;
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}
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};
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char MIRCanonicalizer::ID;
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char &llvm::MIRCanonicalizerID = MIRCanonicalizer::ID;
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INITIALIZE_PASS_BEGIN(MIRCanonicalizer, "mir-canonicalizer",
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"Rename Register Operands Canonically", false, false)
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INITIALIZE_PASS_END(MIRCanonicalizer, "mir-canonicalizer",
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"Rename Register Operands Canonically", false, false)
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static std::vector<MachineBasicBlock *> GetRPOList(MachineFunction &MF) {
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ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
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std::vector<MachineBasicBlock *> RPOList;
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for (auto MBB : RPOT) {
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RPOList.push_back(MBB);
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}
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return RPOList;
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}
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static bool
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rescheduleLexographically(std::vector<MachineInstr *> instructions,
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MachineBasicBlock *MBB,
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std::function<MachineBasicBlock::iterator()> getPos) {
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bool Changed = false;
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using StringInstrPair = std::pair<std::string, MachineInstr *>;
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std::vector<StringInstrPair> StringInstrMap;
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for (auto *II : instructions) {
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std::string S;
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raw_string_ostream OS(S);
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II->print(OS);
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OS.flush();
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// Trim the assignment, or start from the begining in the case of a store.
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const size_t i = S.find("=");
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StringInstrMap.push_back({(i == std::string::npos) ? S : S.substr(i), II});
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}
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llvm::sort(StringInstrMap,
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[](const StringInstrPair &a, const StringInstrPair &b) -> bool {
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return (a.first < b.first);
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});
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for (auto &II : StringInstrMap) {
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LLVM_DEBUG({
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dbgs() << "Splicing ";
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II.second->dump();
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dbgs() << " right before: ";
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getPos()->dump();
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});
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Changed = true;
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MBB->splice(getPos(), MBB, II.second);
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}
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return Changed;
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}
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static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount,
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MachineBasicBlock *MBB) {
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bool Changed = false;
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// Calculates the distance of MI from the begining of its parent BB.
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auto getInstrIdx = [](const MachineInstr &MI) {
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unsigned i = 0;
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for (auto &CurMI : *MI.getParent()) {
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if (&CurMI == &MI)
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return i;
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i++;
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}
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return ~0U;
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};
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// Pre-Populate vector of instructions to reschedule so that we don't
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// clobber the iterator.
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std::vector<MachineInstr *> Instructions;
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for (auto &MI : *MBB) {
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Instructions.push_back(&MI);
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}
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std::map<MachineInstr *, std::vector<MachineInstr *>> MultiUsers;
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std::vector<MachineInstr *> PseudoIdempotentInstructions;
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std::vector<unsigned> PhysRegDefs;
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for (auto *II : Instructions) {
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for (unsigned i = 1; i < II->getNumOperands(); i++) {
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MachineOperand &MO = II->getOperand(i);
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if (!MO.isReg())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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if (!MO.isDef())
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continue;
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PhysRegDefs.push_back(MO.getReg());
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}
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}
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for (auto *II : Instructions) {
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if (II->getNumOperands() == 0)
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continue;
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if (II->mayLoadOrStore())
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continue;
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MachineOperand &MO = II->getOperand(0);
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if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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if (!MO.isDef())
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continue;
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bool IsPseudoIdempotent = true;
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for (unsigned i = 1; i < II->getNumOperands(); i++) {
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if (II->getOperand(i).isImm()) {
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continue;
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}
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if (II->getOperand(i).isReg()) {
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if (!TargetRegisterInfo::isVirtualRegister(II->getOperand(i).getReg()))
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if (llvm::find(PhysRegDefs, II->getOperand(i).getReg()) ==
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PhysRegDefs.end()) {
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continue;
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}
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}
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IsPseudoIdempotent = false;
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break;
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}
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if (IsPseudoIdempotent) {
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PseudoIdempotentInstructions.push_back(II);
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continue;
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}
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LLVM_DEBUG(dbgs() << "Operand " << 0 << " of "; II->dump(); MO.dump(););
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MachineInstr *Def = II;
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unsigned Distance = ~0U;
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MachineInstr *UseToBringDefCloserTo = nullptr;
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MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
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for (auto &UO : MRI->use_nodbg_operands(MO.getReg())) {
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MachineInstr *UseInst = UO.getParent();
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const unsigned DefLoc = getInstrIdx(*Def);
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const unsigned UseLoc = getInstrIdx(*UseInst);
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const unsigned Delta = (UseLoc - DefLoc);
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if (UseInst->getParent() != Def->getParent())
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continue;
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if (DefLoc >= UseLoc)
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continue;
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if (Delta < Distance) {
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Distance = Delta;
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UseToBringDefCloserTo = UseInst;
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}
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}
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const auto BBE = MBB->instr_end();
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MachineBasicBlock::iterator DefI = BBE;
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MachineBasicBlock::iterator UseI = BBE;
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for (auto BBI = MBB->instr_begin(); BBI != BBE; ++BBI) {
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if (DefI != BBE && UseI != BBE)
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break;
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if (&*BBI == Def) {
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DefI = BBI;
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continue;
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}
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if (&*BBI == UseToBringDefCloserTo) {
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UseI = BBI;
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continue;
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}
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}
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if (DefI == BBE || UseI == BBE)
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continue;
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LLVM_DEBUG({
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dbgs() << "Splicing ";
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DefI->dump();
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dbgs() << " right before: ";
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UseI->dump();
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});
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MultiUsers[UseToBringDefCloserTo].push_back(Def);
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Changed = true;
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MBB->splice(UseI, MBB, DefI);
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}
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// Sort the defs for users of multiple defs lexographically.
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for (const auto &E : MultiUsers) {
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auto UseI =
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std::find_if(MBB->instr_begin(), MBB->instr_end(),
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[&](MachineInstr &MI) -> bool { return &MI == E.first; });
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if (UseI == MBB->instr_end())
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continue;
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LLVM_DEBUG(
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dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";);
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Changed |= rescheduleLexographically(
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E.second, MBB, [&]() -> MachineBasicBlock::iterator { return UseI; });
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}
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PseudoIdempotentInstCount = PseudoIdempotentInstructions.size();
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LLVM_DEBUG(
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dbgs() << "Rescheduling Idempotent Instructions Lexographically.";);
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Changed |= rescheduleLexographically(
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PseudoIdempotentInstructions, MBB,
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[&]() -> MachineBasicBlock::iterator { return MBB->begin(); });
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return Changed;
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}
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static bool propagateLocalCopies(MachineBasicBlock *MBB) {
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bool Changed = false;
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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std::vector<MachineInstr *> Copies;
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for (MachineInstr &MI : MBB->instrs()) {
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if (MI.isCopy())
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Copies.push_back(&MI);
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}
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for (MachineInstr *MI : Copies) {
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if (!MI->getOperand(0).isReg())
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continue;
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if (!MI->getOperand(1).isReg())
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continue;
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const unsigned Dst = MI->getOperand(0).getReg();
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const unsigned Src = MI->getOperand(1).getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Dst))
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continue;
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if (!TargetRegisterInfo::isVirtualRegister(Src))
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continue;
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if (MRI.getRegClass(Dst) != MRI.getRegClass(Src))
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continue;
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for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
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MachineOperand *MO = &*UI;
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MO->setReg(Src);
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Changed = true;
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}
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MI->eraseFromParent();
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}
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return Changed;
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}
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/// Here we find our candidates. What makes an interesting candidate?
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/// An candidate for a canonicalization tree root is normally any kind of
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/// instruction that causes side effects such as a store to memory or a copy to
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/// a physical register or a return instruction. We use these as an expression
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/// tree root that we walk inorder to build a canonical walk which should result
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/// in canoncal vreg renaming.
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static std::vector<MachineInstr *> populateCandidates(MachineBasicBlock *MBB) {
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std::vector<MachineInstr *> Candidates;
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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for (auto II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
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MachineInstr *MI = &*II;
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bool DoesMISideEffect = false;
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if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) {
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const unsigned Dst = MI->getOperand(0).getReg();
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DoesMISideEffect |= !TargetRegisterInfo::isVirtualRegister(Dst);
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for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
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if (DoesMISideEffect)
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break;
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DoesMISideEffect |= (UI->getParent()->getParent() != MI->getParent());
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}
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}
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if (!MI->mayStore() && !MI->isBranch() && !DoesMISideEffect)
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continue;
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LLVM_DEBUG(dbgs() << "Found Candidate: "; MI->dump(););
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Candidates.push_back(MI);
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}
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return Candidates;
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}
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static void doCandidateWalk(std::vector<TypedVReg> &VRegs,
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std::queue<TypedVReg> &RegQueue,
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std::vector<MachineInstr *> &VisitedMIs,
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const MachineBasicBlock *MBB) {
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const MachineFunction &MF = *MBB->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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while (!RegQueue.empty()) {
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auto TReg = RegQueue.front();
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RegQueue.pop();
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if (TReg.isFrameIndex()) {
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LLVM_DEBUG(dbgs() << "Popping frame index.\n";);
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VRegs.push_back(TypedVReg(RSE_FrameIndex));
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continue;
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}
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assert(TReg.isReg() && "Expected vreg or physreg.");
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unsigned Reg = TReg.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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LLVM_DEBUG({
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dbgs() << "Popping vreg ";
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MRI.def_begin(Reg)->dump();
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dbgs() << "\n";
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});
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if (!llvm::any_of(VRegs, [&](const TypedVReg &TR) {
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return TR.isReg() && TR.getReg() == Reg;
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})) {
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VRegs.push_back(TypedVReg(Reg));
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}
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} else {
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LLVM_DEBUG(dbgs() << "Popping physreg.\n";);
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VRegs.push_back(TypedVReg(Reg));
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continue;
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}
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for (auto RI = MRI.def_begin(Reg), RE = MRI.def_end(); RI != RE; ++RI) {
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MachineInstr *Def = RI->getParent();
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if (Def->getParent() != MBB)
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continue;
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if (llvm::any_of(VisitedMIs,
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[&](const MachineInstr *VMI) { return Def == VMI; })) {
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break;
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}
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LLVM_DEBUG({
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dbgs() << "\n========================\n";
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dbgs() << "Visited MI: ";
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Def->dump();
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dbgs() << "BB Name: " << Def->getParent()->getName() << "\n";
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dbgs() << "\n========================\n";
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});
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VisitedMIs.push_back(Def);
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for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
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MachineOperand &MO = Def->getOperand(I);
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if (MO.isFI()) {
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LLVM_DEBUG(dbgs() << "Pushing frame index.\n";);
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RegQueue.push(TypedVReg(RSE_FrameIndex));
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}
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if (!MO.isReg())
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continue;
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RegQueue.push(TypedVReg(MO.getReg()));
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}
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}
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}
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}
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namespace {
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class NamedVRegCursor {
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MachineRegisterInfo &MRI;
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unsigned virtualVRegNumber;
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public:
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NamedVRegCursor(MachineRegisterInfo &MRI) : MRI(MRI) {
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unsigned VRegGapIndex = 0;
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const unsigned VR_GAP = (++VRegGapIndex * 1000);
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unsigned I = MRI.createIncompleteVirtualRegister();
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const unsigned E = (((I + VR_GAP) / VR_GAP) + 1) * VR_GAP;
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virtualVRegNumber = E;
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}
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void SkipVRegs() {
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unsigned VRegGapIndex = 1;
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const unsigned VR_GAP = (++VRegGapIndex * 1000);
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unsigned I = virtualVRegNumber;
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const unsigned E = (((I + VR_GAP) / VR_GAP) + 1) * VR_GAP;
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virtualVRegNumber = E;
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}
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unsigned getVirtualVReg() const { return virtualVRegNumber; }
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unsigned incrementVirtualVReg(unsigned incr = 1) {
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virtualVRegNumber += incr;
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return virtualVRegNumber;
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}
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unsigned createVirtualRegister(const TargetRegisterClass *RC) {
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std::string S;
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raw_string_ostream OS(S);
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OS << "namedVReg" << (virtualVRegNumber & ~0x80000000);
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OS.flush();
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virtualVRegNumber++;
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return MRI.createVirtualRegister(RC, OS.str());
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}
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};
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} // namespace
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static std::map<unsigned, unsigned>
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GetVRegRenameMap(const std::vector<TypedVReg> &VRegs,
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const std::vector<unsigned> &renamedInOtherBB,
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MachineRegisterInfo &MRI, NamedVRegCursor &NVC) {
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std::map<unsigned, unsigned> VRegRenameMap;
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bool FirstCandidate = true;
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for (auto &vreg : VRegs) {
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if (vreg.isFrameIndex()) {
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// We skip one vreg for any frame index because there is a good chance
|
|
// (especially when comparing SelectionDAG to GlobalISel generated MIR)
|
|
// that in the other file we are just getting an incoming vreg that comes
|
|
// from a copy from a frame index. So it's safe to skip by one.
|
|
unsigned LastRenameReg = NVC.incrementVirtualVReg();
|
|
(void)LastRenameReg;
|
|
LLVM_DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";);
|
|
continue;
|
|
} else if (vreg.isCandidate()) {
|
|
|
|
// After the first candidate, for every subsequent candidate, we skip mod
|
|
// 10 registers so that the candidates are more likely to start at the
|
|
// same vreg number making it more likely that the canonical walk from the
|
|
// candidate insruction. We don't need to skip from the first candidate of
|
|
// the BasicBlock because we already skip ahead several vregs for each BB.
|
|
unsigned LastRenameReg = NVC.getVirtualVReg();
|
|
if (FirstCandidate)
|
|
NVC.incrementVirtualVReg(LastRenameReg % 10);
|
|
FirstCandidate = false;
|
|
continue;
|
|
} else if (!TargetRegisterInfo::isVirtualRegister(vreg.getReg())) {
|
|
unsigned LastRenameReg = NVC.incrementVirtualVReg();
|
|
(void)LastRenameReg;
|
|
LLVM_DEBUG({
|
|
dbgs() << "Skipping rename for Phys Reg " << LastRenameReg << "\n";
|
|
});
|
|
continue;
|
|
}
|
|
|
|
auto Reg = vreg.getReg();
|
|
if (llvm::find(renamedInOtherBB, Reg) != renamedInOtherBB.end()) {
|
|
LLVM_DEBUG(dbgs() << "Vreg " << Reg
|
|
<< " already renamed in other BB.\n";);
|
|
continue;
|
|
}
|
|
|
|
auto Rename = NVC.createVirtualRegister(MRI.getRegClass(Reg));
|
|
|
|
if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) {
|
|
LLVM_DEBUG(dbgs() << "Mapping vreg ";);
|
|
if (MRI.reg_begin(Reg) != MRI.reg_end()) {
|
|
LLVM_DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump(););
|
|
} else {
|
|
LLVM_DEBUG(dbgs() << Reg;);
|
|
}
|
|
LLVM_DEBUG(dbgs() << " to ";);
|
|
if (MRI.reg_begin(Rename) != MRI.reg_end()) {
|
|
LLVM_DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump(););
|
|
} else {
|
|
LLVM_DEBUG(dbgs() << Rename;);
|
|
}
|
|
LLVM_DEBUG(dbgs() << "\n";);
|
|
|
|
VRegRenameMap.insert(std::pair<unsigned, unsigned>(Reg, Rename));
|
|
}
|
|
}
|
|
|
|
return VRegRenameMap;
|
|
}
|
|
|
|
static bool doVRegRenaming(std::vector<unsigned> &RenamedInOtherBB,
|
|
const std::map<unsigned, unsigned> &VRegRenameMap,
|
|
MachineRegisterInfo &MRI) {
|
|
bool Changed = false;
|
|
for (auto I = VRegRenameMap.begin(), E = VRegRenameMap.end(); I != E; ++I) {
|
|
|
|
auto VReg = I->first;
|
|
auto Rename = I->second;
|
|
|
|
RenamedInOtherBB.push_back(Rename);
|
|
|
|
std::vector<MachineOperand *> RenameMOs;
|
|
for (auto &MO : MRI.reg_operands(VReg)) {
|
|
RenameMOs.push_back(&MO);
|
|
}
|
|
|
|
for (auto *MO : RenameMOs) {
|
|
Changed = true;
|
|
MO->setReg(Rename);
|
|
|
|
if (!MO->isDef())
|
|
MO->setIsKill(false);
|
|
}
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
static bool doDefKillClear(MachineBasicBlock *MBB) {
|
|
bool Changed = false;
|
|
|
|
for (auto &MI : *MBB) {
|
|
for (auto &MO : MI.operands()) {
|
|
if (!MO.isReg())
|
|
continue;
|
|
if (!MO.isDef() && MO.isKill()) {
|
|
Changed = true;
|
|
MO.setIsKill(false);
|
|
}
|
|
|
|
if (MO.isDef() && MO.isDead()) {
|
|
Changed = true;
|
|
MO.setIsDead(false);
|
|
}
|
|
}
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
static bool runOnBasicBlock(MachineBasicBlock *MBB,
|
|
std::vector<StringRef> &bbNames,
|
|
std::vector<unsigned> &renamedInOtherBB,
|
|
unsigned &basicBlockNum, unsigned &VRegGapIndex,
|
|
NamedVRegCursor &NVC) {
|
|
|
|
if (CanonicalizeBasicBlockNumber != ~0U) {
|
|
if (CanonicalizeBasicBlockNumber != basicBlockNum++)
|
|
return false;
|
|
LLVM_DEBUG(dbgs() << "\n Canonicalizing BasicBlock " << MBB->getName()
|
|
<< "\n";);
|
|
}
|
|
|
|
if (llvm::find(bbNames, MBB->getName()) != bbNames.end()) {
|
|
LLVM_DEBUG({
|
|
dbgs() << "Found potentially duplicate BasicBlocks: " << MBB->getName()
|
|
<< "\n";
|
|
});
|
|
return false;
|
|
}
|
|
|
|
LLVM_DEBUG({
|
|
dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << " \n\n";
|
|
dbgs() << "\n\n================================================\n\n";
|
|
});
|
|
|
|
bool Changed = false;
|
|
MachineFunction &MF = *MBB->getParent();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
bbNames.push_back(MBB->getName());
|
|
LLVM_DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";);
|
|
|
|
LLVM_DEBUG(dbgs() << "MBB Before Canonical Copy Propagation:\n";
|
|
MBB->dump(););
|
|
Changed |= propagateLocalCopies(MBB);
|
|
LLVM_DEBUG(dbgs() << "MBB After Canonical Copy Propagation:\n"; MBB->dump(););
|
|
|
|
LLVM_DEBUG(dbgs() << "MBB Before Scheduling:\n"; MBB->dump(););
|
|
unsigned IdempotentInstCount = 0;
|
|
Changed |= rescheduleCanonically(IdempotentInstCount, MBB);
|
|
LLVM_DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump(););
|
|
|
|
std::vector<MachineInstr *> Candidates = populateCandidates(MBB);
|
|
std::vector<MachineInstr *> VisitedMIs;
|
|
llvm::copy(Candidates, std::back_inserter(VisitedMIs));
|
|
|
|
std::vector<TypedVReg> VRegs;
|
|
for (auto candidate : Candidates) {
|
|
VRegs.push_back(TypedVReg(RSE_NewCandidate));
|
|
|
|
std::queue<TypedVReg> RegQueue;
|
|
|
|
// Here we walk the vreg operands of a non-root node along our walk.
|
|
// The root nodes are the original candidates (stores normally).
|
|
// These are normally not the root nodes (except for the case of copies to
|
|
// physical registers).
|
|
for (unsigned i = 1; i < candidate->getNumOperands(); i++) {
|
|
if (candidate->mayStore() || candidate->isBranch())
|
|
break;
|
|
|
|
MachineOperand &MO = candidate->getOperand(i);
|
|
if (!(MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())))
|
|
continue;
|
|
|
|
LLVM_DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";);
|
|
RegQueue.push(TypedVReg(MO.getReg()));
|
|
}
|
|
|
|
// Here we walk the root candidates. We start from the 0th operand because
|
|
// the root is normally a store to a vreg.
|
|
for (unsigned i = 0; i < candidate->getNumOperands(); i++) {
|
|
|
|
if (!candidate->mayStore() && !candidate->isBranch())
|
|
break;
|
|
|
|
MachineOperand &MO = candidate->getOperand(i);
|
|
|
|
// TODO: Do we want to only add vregs here?
|
|
if (!MO.isReg() && !MO.isFI())
|
|
continue;
|
|
|
|
LLVM_DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";);
|
|
|
|
RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg())
|
|
: TypedVReg(RSE_FrameIndex));
|
|
}
|
|
|
|
doCandidateWalk(VRegs, RegQueue, VisitedMIs, MBB);
|
|
}
|
|
|
|
// If we have populated no vregs to rename then bail.
|
|
// The rest of this function does the vreg remaping.
|
|
if (VRegs.size() == 0)
|
|
return Changed;
|
|
|
|
auto VRegRenameMap = GetVRegRenameMap(VRegs, renamedInOtherBB, MRI, NVC);
|
|
Changed |= doVRegRenaming(renamedInOtherBB, VRegRenameMap, MRI);
|
|
|
|
// Here we renumber the def vregs for the idempotent instructions from the top
|
|
// of the MachineBasicBlock so that they are named in the order that we sorted
|
|
// them alphabetically. Eventually we wont need SkipVRegs because we will use
|
|
// named vregs instead.
|
|
NVC.SkipVRegs();
|
|
|
|
auto MII = MBB->begin();
|
|
for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {
|
|
MachineInstr &MI = *MII++;
|
|
Changed = true;
|
|
unsigned vRegToRename = MI.getOperand(0).getReg();
|
|
auto Rename = NVC.createVirtualRegister(MRI.getRegClass(vRegToRename));
|
|
|
|
std::vector<MachineOperand *> RenameMOs;
|
|
for (auto &MO : MRI.reg_operands(vRegToRename)) {
|
|
RenameMOs.push_back(&MO);
|
|
}
|
|
|
|
for (auto *MO : RenameMOs) {
|
|
MO->setReg(Rename);
|
|
}
|
|
}
|
|
|
|
Changed |= doDefKillClear(MBB);
|
|
|
|
LLVM_DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump();
|
|
dbgs() << "\n";);
|
|
LLVM_DEBUG(
|
|
dbgs() << "\n\n================================================\n\n");
|
|
return Changed;
|
|
}
|
|
|
|
bool MIRCanonicalizer::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
static unsigned functionNum = 0;
|
|
if (CanonicalizeFunctionNumber != ~0U) {
|
|
if (CanonicalizeFunctionNumber != functionNum++)
|
|
return false;
|
|
LLVM_DEBUG(dbgs() << "\n Canonicalizing Function " << MF.getName()
|
|
<< "\n";);
|
|
}
|
|
|
|
// we need a valid vreg to create a vreg type for skipping all those
|
|
// stray vreg numbers so reach alignment/canonical vreg values.
|
|
std::vector<MachineBasicBlock *> RPOList = GetRPOList(MF);
|
|
|
|
LLVM_DEBUG(
|
|
dbgs() << "\n\n NEW MACHINE FUNCTION: " << MF.getName() << " \n\n";
|
|
dbgs() << "\n\n================================================\n\n";
|
|
dbgs() << "Total Basic Blocks: " << RPOList.size() << "\n";
|
|
for (auto MBB
|
|
: RPOList) { dbgs() << MBB->getName() << "\n"; } dbgs()
|
|
<< "\n\n================================================\n\n";);
|
|
|
|
std::vector<StringRef> BBNames;
|
|
std::vector<unsigned> RenamedInOtherBB;
|
|
|
|
unsigned GapIdx = 0;
|
|
unsigned BBNum = 0;
|
|
|
|
bool Changed = false;
|
|
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
NamedVRegCursor NVC(MRI);
|
|
for (auto MBB : RPOList)
|
|
Changed |=
|
|
runOnBasicBlock(MBB, BBNames, RenamedInOtherBB, BBNum, GapIdx, NVC);
|
|
|
|
return Changed;
|
|
}
|