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121 lines
3.4 KiB
ReStructuredText
121 lines
3.4 KiB
ReStructuredText
==============================
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User Guide for AMDGPU Back-end
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==============================
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Introduction
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============
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The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with
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the R600 family up until the current Volcanic Islands (GCN Gen 3).
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Assembler
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=========
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The assembler is currently considered experimental.
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For syntax examples look in test/MC/AMDGPU.
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Below some of the currently supported features (modulo bugs). These
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all apply to the Southern Islands ISA, Sea Islands and Volcanic Islands
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are also supported but may be missing some instructions and have more bugs:
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DS Instructions
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---------------
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All DS instructions are supported.
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FLAT Instructions
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------------------
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These instructions are only present in the Sea Islands and Volcanic Islands
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instruction set. All FLAT instructions are supported for these architectures
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MUBUF Instructions
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------------------
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All non-atomic MUBUF instructions are supported.
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SMRD Instructions
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-----------------
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Only the s_load_dword* SMRD instructions are supported.
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SOP1 Instructions
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-----------------
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All SOP1 instructions are supported.
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SOP2 Instructions
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-----------------
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All SOP2 instructions are supported.
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SOPC Instructions
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-----------------
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All SOPC instructions are supported.
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SOPP Instructions
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-----------------
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Unless otherwise mentioned, all SOPP instructions that have one or more
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operands accept integer operands only. No verification is performed
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on the operands, so it is up to the programmer to be familiar with the
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range or acceptable values.
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s_waitcnt
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^^^^^^^^^
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s_waitcnt accepts named arguments to specify which memory counter(s) to
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wait for.
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.. code-block:: nasm
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// Wait for all counters to be 0
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s_waitcnt 0
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// Equivalent to s_waitcnt 0. Counter names can also be delimited by
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// '&' or ','.
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s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0)
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// Wait for vmcnt counter to be 1.
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s_waitcnt vmcnt(1)
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VOP1, VOP2, VOP3, VOPC Instructions
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-----------------------------------
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All 32-bit and 64-bit encodings should work.
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The assembler will automatically detect which encoding size to use for
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VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
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a specific encoding size, you can add an _e32 (for 32-bit encoding) or
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_e64 (for 64-bit encoding) suffix to the instruction. Most, but not all
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instructions support an explicit suffix. These are all valid assembly
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strings:
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.. code-block:: nasm
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v_mul_i32_i24 v1, v2, v3
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v_mul_i32_i24_e32 v1, v2, v3
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v_mul_i32_i24_e64 v1, v2, v3
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Assembler Directives
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--------------------
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.hsa_code_object_version major, minor
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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*major* and *minor* are integers that specify the version of the HSA code
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object that will be generated by the assembler. This value will be stored
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in an entry of the .note section.
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.hsa_code_object_isa [major, minor, stepping, vendor, arch]
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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*major*, *minor*, and *stepping* are all integers that describe the instruction
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set architecture (ISA) version of the assembly program.
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*vendor* and *arch* are quoted strings. *vendor* should always be equal to
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"AMD" and *arch* should always be equal to "AMDGPU".
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If no arguments are specified, then the assembler will derive the ISA version,
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*vendor*, and *arch* from the value of the -mcpu option that is passed to the
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assembler.
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ISA version, *vendor*, and *arch* will all be stored in a single entry of the
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.note section.
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