Rafael Espindola 9c3d5a70f4 Now that RegistersDefinedFromSameValue handles one instruction being an ...

implicit_def, the other instruction can be anything, including instructions
that define multiple values. Be careful about that and don't assume what operand
0 is.
Fixes pr13249.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159509 91177308-0d34-0410-b5e6-96231b3b80d8

2012-07-01 17:08:01 +00:00

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ARM

Now that RegistersDefinedFromSameValue handles one instruction being an

2012-07-01 17:08:01 +00:00

CellSPU

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CPP

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Generic

add a new @llvm.donothing intrinsic that, well, does nothing, and teach CodeGen to ignore calls to it

2012-06-28 22:30:12 +00:00

Hexagon

Enable all Hexagon tests.

2012-05-15 16:13:12 +00:00

MBlaze

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Mips

The Mips specific inline asm operand modifier 'z' has the

2012-06-28 01:33:40 +00:00

MSP430

These tests used intrinsics with the wrong prototype. They weren't caught because

2012-05-27 19:35:41 +00:00

NVPTX

Add llvm.fabs intrinsic.

2012-05-28 21:48:37 +00:00

PowerPC

Add support for the PPC isel instruction.

2012-06-22 23:10:08 +00:00

SPARC

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Thumb

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Thumb2

Add a test case for global live range splitting.

2012-05-23 23:42:23 +00:00

X86

Optimization of shuffle node that can fit to the register form of VBROADCAST instruction on AVX2.

2012-07-01 06:12:26 +00:00

XCore

Fix pattern for MKMSK instruction.

2012-06-13 17:59:12 +00:00