llvm/lib/CodeGen
Arnaud A. de Grandmaison 8025a39d11 [PBQP] Tweak spill costs and coalescing benefits
This patch improves how the different costs (register, interference, spill
and coalescing) relates together. The assumption is now that:
 - coalescing (or any other "side effect" of reg alloc) is negative, and
   instead of being derived from a spill cost, they use the block
   frequency info.
 - spill costs are in the [MinSpillCost:+inf( range
 - register or interference costs are in [0.0:MinSpillCost( or +inf

The current MinSpillCost is set to 10.0, which is a random value high
enough that the current constraint builders do not need to worry about
when settings costs. It would however be worth adding a normalization
step for register and interference costs as the last step in the
constraint builder chain to ensure they are not greater than SpillMinCost
(unless this has some sense for some architectures). This would work well
with the current builder pipeline, where all costs are tweaked relatively
to each others, but could grow above MinSpillCost if the pipeline is
deep enough.

The current heuristic is tuned to depend rather on the number of uses of
a live interval rather than a density of uses, as used by the greedy
allocator. This heuristic provides a few percent improvement on a number
of benchmarks (eembc, spec, ...) and will definitely need to change once
spill placement is implemented: the current spill placement is really
ineficient, so making the cost proportionnal to the number of use is a
clear win.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04 20:51:24 +00:00
..
AsmPrinter CodeGen: Enable DWARF emission for MS ABI targets 2014-11-04 08:03:31 +00:00
SelectionDAG Normally an 'optnone' function goes through fast-isel, which does not 2014-11-03 18:19:26 +00:00
AggressiveAntiDepBreaker.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
AggressiveAntiDepBreaker.h mop up: "Don’t duplicate function or class name at the beginning of the comment." 2014-09-21 14:48:16 +00:00
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp
AntiDepBreaker.h mop up: "Don’t duplicate function or class name at the beginning of the comment." 2014-09-21 14:48:16 +00:00
AtomicExpandPass.cpp Lower idempotent RMWs to fence+load 2014-09-25 17:27:43 +00:00
BasicTargetTransformInfo.cpp Fix typo 2014-10-22 00:28:59 +00:00
BranchFolding.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
BranchFolding.h
CalcSpillWeights.cpp [PBQP] Tweak spill costs and coalescing benefits 2014-11-04 20:51:24 +00:00
CallingConvLower.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
CMakeLists.txt [MCJIT] Nuke MachineRelocation and MachineCodeEmitter. Now that the old JIT is 2014-09-23 18:08:47 +00:00
CodeGen.cpp
CodeGenPrepare.cpp [CodeGenPrepare] Move extractelement close to store if they can be combined. 2014-10-31 17:52:53 +00:00
CriticalAntiDepBreaker.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
CriticalAntiDepBreaker.h mop up: "Don’t duplicate function or class name at the beginning of the comment." 2014-09-21 14:48:16 +00:00
DeadMachineInstructionElim.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
DFAPacketizer.cpp Remove the TargetMachine from DFAPacketizer since it was only 2014-10-14 01:03:16 +00:00
DwarfEHPrepare.cpp In DwarfEHPrepare, after all passes are run, RewindFunction may be a dangling 2014-09-14 20:36:28 +00:00
EarlyIfConversion.cpp Change MCSchedModel to be a struct of statically initialized data. 2014-09-02 17:43:54 +00:00
EdgeBundles.cpp
ErlangGC.cpp
ExecutionDepsFix.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
ExpandISelPseudos.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
ExpandPostRAPseudos.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
GlobalMerge.cpp
IfConversion.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
InlineSpiller.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
InterferenceCache.cpp
InterferenceCache.h
IntrinsicLowering.cpp [PATCH][Interpreter] Add missing FP intrinsic lowering. 2014-08-30 18:33:35 +00:00
JumpInstrTables.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself. 2014-10-14 18:22:52 +00:00
LiveDebugVariables.cpp Added reset of LexicalScope in LiveDebugVariables reset function. 2014-10-24 02:46:50 +00:00
LiveDebugVariables.h
LiveInterval.cpp
LiveIntervalAnalysis.cpp Access the subtarget off of the MachineFunction rather than 2014-10-14 06:26:53 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp
LiveRangeCalc.cpp
LiveRangeCalc.h
LiveRangeEdit.cpp
LiveRegMatrix.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Simplify handling of --noexecstack by using getNonexecutableStackSection. 2014-10-15 16:12:52 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp
MachineBranchProbabilityInfo.cpp
MachineCombiner.cpp Change MCSchedModel to be a struct of statically initialized data. 2014-09-02 17:43:54 +00:00
MachineCopyPropagation.cpp
MachineCSE.cpp
MachineDominanceFrontier.cpp
MachineDominators.cpp
MachineFunction.cpp Remove unused member variable. 2014-10-14 18:53:16 +00:00
MachineFunctionAnalysis.cpp Remove unused member variable. 2014-10-14 18:53:16 +00:00
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
MachineInstrBundle.cpp Have MachineInstrBundle use the MachineFunction for subtarget 2014-10-14 06:26:55 +00:00
MachineLICM.cpp Remove the use and member variable of the TargetMachine from 2014-10-14 06:26:57 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp
MachineScheduler.cpp Access the subtarget off of the MachineFunction via the DAG 2014-10-14 06:56:25 +00:00
MachineSink.cpp [MachineSink] Use the real post dominator tree 2014-10-15 03:27:43 +00:00
MachineSSAUpdater.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
MachineTraceMetrics.cpp Change MCSchedModel to be a struct of statically initialized data. 2014-09-02 17:43:54 +00:00
MachineVerifier.cpp Access subtarget specific variables off of the MachineFunction's 2014-10-14 07:00:33 +00:00
Makefile
module.modulemap
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Pacify bots and simplify r220321 2014-10-21 21:50:49 +00:00
PeepholeOptimizer.cpp Avoid caching the MachineFunction, we don't use it outside of 2014-10-15 21:06:25 +00:00
PHIElimination.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Whitespace. 2014-10-29 15:23:11 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Grab the subtarget and subtarget dependent variables off of 2014-10-14 07:17:23 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
RegAllocBase.h
RegAllocBasic.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
RegAllocFast.cpp Grab the subtarget and subtarget dependent variables off of 2014-10-14 07:22:00 +00:00
RegAllocGreedy.cpp [PBQP] Tweak spill costs and coalescing benefits 2014-11-04 20:51:24 +00:00
RegAllocPBQP.cpp [PBQP] Tweak spill costs and coalescing benefits 2014-11-04 20:51:24 +00:00
RegisterClassInfo.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
RegisterCoalescer.cpp delete function names from comments 2014-10-09 21:24:46 +00:00
RegisterCoalescer.h mop up: "Don’t duplicate function or class name at the beginning of the comment." 2014-09-20 22:39:16 +00:00
RegisterPressure.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
RegisterScavenging.cpp Grab the subtarget and subtarget dependent variables off of 2014-10-14 07:22:00 +00:00
ScheduleDAG.cpp
ScheduleDAGInstrs.cpp Remove an unnecessary restriction. MIsNeedChainEdge() should be checked even when scheduler AliasAnalysis is not 2014-09-12 21:17:55 +00:00
ScheduleDAGPrinter.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
ScoreboardHazardRecognizer.cpp Change MCSchedModel to be a struct of statically initialized data. 2014-09-02 17:43:54 +00:00
ShadowStackGC.cpp
SjLjEHPrepare.cpp
SlotIndexes.cpp
Spiller.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
Spiller.h
SpillPlacement.cpp Fix the threshold added in r186434 (a re-apply of r185393) and updaated 2014-10-02 22:23:14 +00:00
SpillPlacement.h Fix the threshold added in r186434 (a re-apply of r185393) and updaated 2014-10-02 22:23:14 +00:00
SplitKit.cpp Grab the subtarget and subtarget dependent variables off of 2014-10-14 07:22:00 +00:00
SplitKit.h
StackColoring.cpp Fix typos in comments, NFC 2014-08-29 21:53:01 +00:00
StackMapLivenessAnalysis.cpp
StackMaps.cpp The patchpoint lowering logic would crash with live constants equal to 2014-11-04 00:59:21 +00:00
StackProtector.cpp
StackSlotColoring.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
TailDuplication.cpp
TargetFrameLoweringImpl.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
TargetInstrInfo.cpp Fix a lot of confusion around inserting nops on empty functions. 2014-09-15 18:32:58 +00:00
TargetLoweringBase.cpp PR20557: Fix the bug that bogus cpu parameter crashes llc on AArch64 backend. 2014-10-31 02:35:34 +00:00
TargetLoweringObjectFileImpl.cpp MC: ReadOnlyWithRel section kinds should map to rdata in COFF 2014-09-22 20:39:23 +00:00
TargetOptionsImpl.cpp
TargetRegisterInfo.cpp
TargetSchedule.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp
VirtRegMap.cpp Migrate another set of getSubtargetImpl away. 2014-10-13 21:57:44 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.