Andrew Trick 81349a7435 Track IR ordering of SelectionDAG nodes 4/4. ...

Unit test cases for -pre-RA-sched=source.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182706 91177308-0d34-0410-b5e6-96231b3b80d8

2013-05-25 03:26:51 +00:00

..

AArch64

Track IR ordering of SelectionDAG nodes 3/4.

2013-05-25 03:08:10 +00:00

ARM

Track IR ordering of SelectionDAG nodes 4/4.

2013-05-25 03:26:51 +00:00

CPP

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Generic

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

2013-05-21 14:37:16 +00:00

Hexagon

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

Inputs

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MBlaze

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Mips

Track IR ordering of SelectionDAG nodes 4/4.

2013-05-25 03:26:51 +00:00

MSP430

DAGCombiner: Simplify inverted bit tests

2013-05-08 06:44:42 +00:00

NVPTX

[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic

2013-05-21 16:51:30 +00:00

PowerPC

PPC: Initial support for permutation-based unaligned Altivec loads

2013-05-24 23:00:14 +00:00

R600

R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg

2013-05-23 18:26:42 +00:00

SI

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SPARC

Also expand 64-bit bitcasts.

2013-05-20 01:01:43 +00:00

SystemZ

[SystemZ] Tighten branch tests

2013-05-21 08:53:17 +00:00

Thumb

LocalStackSlotAllocation improvements

2013-04-30 20:04:37 +00:00

Thumb2

Fix ARM FastISel tests, as a first step to enabling ARM FastISel

2013-05-14 16:26:38 +00:00

X86

Track IR ordering of SelectionDAG nodes 4/4.

2013-05-25 03:26:51 +00:00

XCore

[XCore] Fix handling of functions where only the LR is spilled.

2013-05-09 16:43:42 +00:00