Bob Wilson 815baebe1c Change ARM ld/st multiple instructions to have variant instructions for ... writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8		2010-03-13 01:08:20 +00:00
..
Analysis	Do not ignore arg_size() impact while counting bb instructions.	2010-03-13 01:05:02 +00:00
Archive
AsmParser
Bitcode
CodeGen	remove gone method, grr symlinks.	2010-03-12 21:30:49 +00:00
CompilerDriver
ExecutionEngine	Add a new jump table encoding to indicate jump tables entries	2010-03-11 14:58:16 +00:00
Linker
MC	MC/Mach-O: Implement initial support for relaxation.	2010-03-12 22:07:14 +00:00
Support
System	Remove superfluous NULL assignment	2010-03-12 14:17:24 +00:00
Target	Change ARM ld/st multiple instructions to have variant instructions for	2010-03-13 01:08:20 +00:00
Transforms	Add a virtual destructor and give vtable a home.	2010-03-12 20:41:29 +00:00
VMCore	Remove duplicated code. No functionality change.	2010-03-10 16:04:20 +00:00
Makefile