Craig Topper 835e7bc48e Recommit r171461 which was incorrectly reverted. Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171608 91177308-0d34-0410-b5e6-96231b3b80d8

2013-01-05 07:39:25 +00:00

..

ARM

Revert "Adding support for llvm.arm.neon.vaddl[su].* and"

2012-12-20 21:09:38 +00:00

CPP

test commit

2012-07-18 17:53:05 +00:00

Generic

After reducing the size of an operation in the DAG we zero-extend the reduced

2012-12-19 07:39:08 +00:00

Hexagon

In hexagon convertToHardwareLoop, don't deref end() iterator

2012-12-07 21:03:15 +00:00

MBlaze

Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu

2012-03-25 09:02:19 +00:00

Mips

[mips] MipsTargetLowering::getSetCCResultType should return a vector type if

2013-01-04 20:06:01 +00:00

MSP430

Add support for varargs functions for msp430.

2012-11-21 17:28:27 +00:00

NVPTX

[NVPTX] Fix crash with unnamed struct arguments

2012-12-05 20:50:28 +00:00

PowerPC

Support ppcf128 in SelectionDAG::getConstantFP

2012-12-30 19:03:32 +00:00

R600

DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes

2013-01-02 22:13:01 +00:00

SI

Add R600 backend

2012-12-11 21:25:42 +00:00

SPARC

Use TargetTransformInfo to control switch-to-lookup table transformation

2012-10-30 11:23:25 +00:00

Thumb

Use the 'count' attribute to calculate the upper bound of an array.

2012-12-04 21:34:03 +00:00

Thumb2

On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,

2012-12-20 19:59:30 +00:00

X86

Recommit r171461 which was incorrectly reverted. Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks.

2013-01-05 07:39:25 +00:00

XCore

Fix handling of aliases to functions.

2012-11-16 21:12:38 +00:00