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https://github.com/RPCS3/llvm.git
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922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
153 lines
3.5 KiB
LLVM
153 lines
3.5 KiB
LLVM
; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux -join-physregs | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mcpu=generic -mtriple=x86_64-win32 -join-physregs | FileCheck %s -check-prefix=X64
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; Some of these tests depend on -join-physregs to commute instructions.
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; The immediate can be encoded in a smaller way if the
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; instruction is a sub instead of an add.
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define i32 @test1(i32 inreg %a) nounwind {
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%b = add i32 %a, 128
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ret i32 %b
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; X32: subl $-128, %eax
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; X64: subl $-128,
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}
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define i64 @test2(i64 inreg %a) nounwind {
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%b = add i64 %a, 2147483648
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ret i64 %b
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; X32: addl $-2147483648, %eax
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; X64: subq $-2147483648,
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}
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define i64 @test3(i64 inreg %a) nounwind {
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%b = add i64 %a, 128
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ret i64 %b
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; X32: addl $128, %eax
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; X64: subq $-128,
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}
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define i1 @test4(i32 %v1, i32 %v2, i32* %X) nounwind {
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entry:
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%sum = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %overflow, label %normal
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normal:
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store i32 0, i32* %X
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br label %overflow
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overflow:
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ret i1 false
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; X32: test4:
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; X32: addl
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; X32-NEXT: jo
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; X64: test4:
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; X64: addl %e[[A1:si|dx]], %e[[A0:di|cx]]
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; X64-NEXT: jo
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}
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define i1 @test5(i32 %v1, i32 %v2, i32* %X) nounwind {
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entry:
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%sum = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %carry, label %normal
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normal:
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store i32 0, i32* %X
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br label %carry
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carry:
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ret i1 false
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; X32: test5:
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; X32: addl
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; X32-NEXT: jb
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; X64: test5:
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; X64: addl %e[[A1]], %e[[A0]]
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; X64-NEXT: jb
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}
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declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
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declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
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define i64 @test6(i64 %A, i32 %B) nounwind {
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%tmp12 = zext i32 %B to i64 ; <i64> [#uses=1]
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%tmp3 = shl i64 %tmp12, 32 ; <i64> [#uses=1]
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%tmp5 = add i64 %tmp3, %A ; <i64> [#uses=1]
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ret i64 %tmp5
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; X32: test6:
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; X32: movl 12(%esp), %edx
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; X32-NEXT: addl 8(%esp), %edx
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; X32-NEXT: movl 4(%esp), %eax
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; X32-NEXT: ret
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; X64: test6:
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; X64: shlq $32, %r[[A1]]
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; X64: leaq (%r[[A1]],%r[[A0]]), %rax
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; X64: ret
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}
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define {i32, i1} @test7(i32 %v1, i32 %v2) nounwind {
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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ret {i32, i1} %t
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}
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; X64: test7:
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; X64: addl %e[[A1]], %eax
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; X64-NEXT: setb %dl
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; X64-NEXT: ret
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; PR5443
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define {i64, i1} @test8(i64 %left, i64 %right) nounwind {
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entry:
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%extleft = zext i64 %left to i65
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%extright = zext i64 %right to i65
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%sum = add i65 %extleft, %extright
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%res.0 = trunc i65 %sum to i64
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%overflow = and i65 %sum, -18446744073709551616
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%res.1 = icmp ne i65 %overflow, 0
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%final0 = insertvalue {i64, i1} undef, i64 %res.0, 0
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%final1 = insertvalue {i64, i1} %final0, i1 %res.1, 1
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ret {i64, i1} %final1
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}
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; X64: test8:
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; X64: addq
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; X64-NEXT: sbbq
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; X64-NEXT: testb
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define i32 @test9(i32 %x, i32 %y) nounwind readnone {
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%cmp = icmp eq i32 %x, 10
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%sub = sext i1 %cmp to i32
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%cond = add i32 %sub, %y
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ret i32 %cond
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; X64: test9:
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; X64: cmpl $10
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; X64: sete
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; X64: subl
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; X64: ret
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}
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define i1 @test10(i32 %x) nounwind {
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entry:
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %x, i32 1)
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%obit = extractvalue {i32, i1} %t, 1
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ret i1 %obit
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; X32: test10:
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; X32: incl
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; X32-NEXT: seto
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; X64: test10:
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; X64: incl
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; X64-NEXT: seto
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}
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