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llvm/test/Transforms/InstCombine/assume2.ll
Sanjay Patel dc1b8f4271 [InstCombine] don't use DeMorgan's Law on integer constants (2nd try) 
This was originally checked in here:
https://reviews.llvm.org/rL301923

And reverted here:
https://reviews.llvm.org/rL301924

Because there's a clang test that would fail after this. I fixed/removed the
offending CHECK lines in:
https://reviews.llvm.org/rL301928

So let's try this again. Original commit message:

This is the fold that causes the infinite loop in BoringSSL
(https://github.com/google/boringssl/blob/master/crypto/cipher/e_rc2.c)
when we fix instcombine demanded bits to prefer 'not' ops as in https://reviews.llvm.org/D32255.

There are 2 or 3 problems with dyn_castNotVal, and I don't think we can
reinstate https://reviews.llvm.org/D32255 until dyn_castNotVal is completely eliminated.

1. As shown here, it transforms 'not' into random xor. This transform is harmful to SCEV and codegen because 'not' can often be folded while random xor cannot.
2. It does not transform vector constants. This is actually a good thing, but if you don't believe the above argument, then we shouldn't have excluded vectors.
3. It tries to avoid transforming not(not(X)). That's nice, but it doesn't match the greedy nature of instcombine. If we DeMorganize a pattern that has an extra 'not' in it: ~(~(~X) & Y) --> (~X | ~Y)

  That's just another case of DeMorgan, so we should trust that we'll fold that pattern too: (~X | ~ Y) --> ~(X & Y)

Differential Revision: https://reviews.llvm.org/D32665



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301929 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-02 15:31:40 +00:00

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
declare void @llvm.assume(i1) #1
define i32 @test1(i32 %a) #0 {
; CHECK-LABEL: @test1(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], 15
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 5
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 5
;
%and = and i32 %a, 15
%cmp = icmp eq i32 %and, 5
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 7
ret i32 %and1
}
define i32 @test2(i32 %a) #0 {
; CHECK-LABEL: @test2(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], 15
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 10
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 2
;
%and = and i32 %a, 15
%nand = xor i32 %and, -1
%cmp = icmp eq i32 %nand, 4294967285
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 7
ret i32 %and1
}
define i32 @test3(i32 %a) #0 {
; CHECK-LABEL: @test3(
; CHECK-NEXT: [[V:%.*]] = or i32 [[A:%.*]], -16
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V]], -11
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 5
;
%v = or i32 %a, 4294967280
%cmp = icmp eq i32 %v, 4294967285
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 7
ret i32 %and1
}
define i32 @test4(i32 %a) #0 {
; CHECK-LABEL: @test4(
; CHECK-NEXT: [[V:%.*]] = or i32 [[A:%.*]], -16
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V]], -6
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 2
;
%v = or i32 %a, 4294967280
%nv = xor i32 %v, -1
%cmp = icmp eq i32 %nv, 5
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 7
ret i32 %and1
}
define i32 @test5(i32 %a) #0 {
; CHECK-LABEL: @test5(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 4
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 4
;
%v = xor i32 %a, 1
%cmp = icmp eq i32 %v, 5
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 7
ret i32 %and1
}
define i32 @test6(i32 %a) #0 {
; CHECK-LABEL: @test6(
; CHECK-NEXT: [[V_MASK:%.*]] = and i32 [[A:%.*]], 1073741823
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V_MASK]], 5
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 5
;
%v = shl i32 %a, 2
%cmp = icmp eq i32 %v, 20
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 63
ret i32 %and1
}
define i32 @test7(i32 %a) #0 {
; CHECK-LABEL: @test7(
; CHECK-NEXT: [[V_MASK:%.*]] = and i32 [[A:%.*]], -4
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V_MASK]], 20
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 20
;
%v = lshr i32 %a, 2
%cmp = icmp eq i32 %v, 5
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 252
ret i32 %and1
}
define i32 @test8(i32 %a) #0 {
; CHECK-LABEL: @test8(
; CHECK-NEXT: [[V_MASK:%.*]] = and i32 [[A:%.*]], -4
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V_MASK]], 20
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 20
;
%v = lshr i32 %a, 2
%cmp = icmp eq i32 %v, 5
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 252
ret i32 %and1
}
define i32 @test9(i32 %a) #0 {
; CHECK-LABEL: @test9(
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A:%.*]], 5
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 0
;
%cmp = icmp sgt i32 %a, 5
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 2147483648
ret i32 %and1
}
define i32 @test10(i32 %a) #0 {
; CHECK-LABEL: @test10(
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A:%.*]], -1
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 -2147483648
;
%cmp = icmp sle i32 %a, -2
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 2147483648
ret i32 %and1
}
define i32 @test11(i32 %a) #0 {
; CHECK-LABEL: @test11(
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[A:%.*]], 257
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret i32 0
;
%cmp = icmp ule i32 %a, 256
tail call void @llvm.assume(i1 %cmp)
%and1 = and i32 %a, 3072
ret i32 %and1
}
attributes #0 = { nounwind uwtable }
attributes #1 = { nounwind }
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