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https://github.com/RPCS3/llvm.git
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Tony Jiang
758e067345
Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292154 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.4 KiB
LLVM
36 lines
1.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -ppc-gen-isel=false < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @test(i64 %x) nounwind readnone {
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entry:
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%conv = sitofp i64 %x to float
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ret float %conv
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}
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; Verify that we get the code sequence needed to avoid double-rounding.
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; Note that only parts of the sequence are checked for here, to allow
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; for minor code generation differences.
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;CHECK-LABEL: test
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;CHECK-NO-ISEL-LABEL: test
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; CHECK: sradi [[REG1:[0-9]+]], 3, 53
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; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
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; CHECK: cmpldi [[REG2]], 1
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; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
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; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
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; CHECK-NO-ISEL: ori 11, 3, 0
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; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
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; CHECK-NO-ISEL-NEXT: [[TRUE]]
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; CHECK-NO-ISEL-NEXT: addi 11, 4, 0
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; CHECK: std [[REG3]], -{{[0-9]+}}(1)
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; Also check that with -enable-unsafe-fp-math we do not get that extra
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; code sequence. Simply verify that there is no "isel" present.
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE
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; CHECK-UNSAFE-NOT: isel
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